Slot-shielded coplanar strip-line compatible with CMOS processes

Patent metadata

Field	Value
Publication number	US-9831173-B2
Application number	US-201514802267-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Nov 1, 2010
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate;
a ground plane overlying the semiconductor substrate, wherein the ground plane is grounded;
a first signal line over the semiconductor substrate and parallel to the ground plane;
a plurality of p-well strips in the semiconductor substrate;
a plurality of n-well strips in the semiconductor substrate, with the plurality of p-well strips and the plurality of n-well strips disposed in an alternating layout, wherein each of the plurality of p-well strips and the plurality of n-well strips comprises a first portion overlapped by a portion of the first signal line and a second portion overlapped by a portion of the ground plane; and
electrical connections electrically coupling the plurality of p-well strips and the plurality of n-well strips to the ground plane.

2. The device of claim 1 further comprising a plurality of vias, each electrically coupling the ground plane to one of the plurality of n-well strips and the plurality of p-well strips.

3. The device of claim 1 further comprising a second signal line on an opposite side of the ground plane than the first signal line, wherein the first signal line and the second signal line are differential signal lines carrying differential signals.

4. The device of claim 1 further comprising a second signal line on an opposite side of the ground plane than the first signal line, wherein an end of the first signal line is connected to an end of the second signal line.

5. The device of claim 1 further comprising a well region underlying, and contacting, the plurality of p-well strips and the plurality of n-well strips.

6. The device of claim 5 , wherein a bottom of the well region contacts a portion of the semiconductor substrate that is of a first conductivity type opposite to a second conductivity type of the well region.

7. The device of claim 5 further comprising an additional well region between and contacting the well region and the semiconductor substrate, wherein the well region and the semiconductor substrate are of a same conductivity type, and the additional well region and the semiconductor substrate are of opposite conductivity types.

8. A device comprising:
a semiconductor substrate;
a ground plane overlying the semiconductor substrate;
a first signal line and a second signal line on opposite sides of, and parallel to, the ground plane, wherein the first signal line and the second signal line are overlying the semiconductor substrate;
a plurality of p-well strips in the semiconductor substrate; and
a plurality of n-well strips, each disposed in a space between two neighboring ones of the plurality of p-well strips, wherein each of the plurality of p-well strips and the plurality of n-well strips comprises a first portion vertically overlapped by a portion of the first signal line and a second portion vertically overlapped by a portion of the ground plane.

9. The device of claim 8 , wherein the first signal line and the second signal line are differential signal lines carrying differential signals.

10. The device of claim 8 , wherein an end of the first signal line is connected to an end of the second signal line.

11. The device of claim 8 , wherein each of the plurality of n-well strips physically contacts edges of the two neighboring ones of the plurality of p-well strips.

12. The device of claim 8 , wherein the plurality of p-well strips and the plurality of n-well strips are electrically grounded.

13. The device of claim 8 , wherein the plurality of p-well strips and the plurality of n-well strips in combination forms a continuous region.

14. The device of claim 8 , wherein the ground plane extends into a plurality of metal layers.

15. The device of claim 8 further comprising a plurality of vias, each physically connects the ground plane to one of the plurality of n-well strips and the plurality of p-well strips.

16. A device comprising:
a semiconductor substrate;
a ground plane overlying the semiconductor substrate, wherein the ground plane is electrically grounded, and in a top view of the device, the ground plane is elongated, and has a first lengthwise direction;
a plurality of p-well strips in the semiconductor substrate;
a plurality of n-well strips, each disposed in a space between two neighboring ones of the plurality of p-well strips, wherein the plurality of n-well strips is in the semiconductor substrate, and the plurality of p-well strips and the plurality of n-well strips are elongated in the top view and have second lengthwise directions parallel to each other, and the second lengthwise directions are perpendicular to the first lengthwise direction;
a first plurality of vias, each electrically connecting the ground plane to one of the plurality of p-well strips; and
a second plurality of vias, each electrically connecting the ground plane to one of the plurality of n-well strips.

17. The device of claim 16 further comprising a first signal line parallel to the ground plane, wherein the first signal line overlaps both the plurality of p-well strips and the plurality of n-well strips.

18. The device of claim 17 further comprising a second signal line on an opposite side of the ground plane than the first signal line, wherein the first signal line and the second signal line are differential signal lines carrying differential signals.

19. The device of claim 18 , wherein an end of the first signal line is connected to an end of the second signal line.

20. The device of claim 16 , wherein the ground plane comprises portions extending into a plurality of metal layers over the semiconductor substrate, with the portions aligned to a vertical plane perpendicular to a major top surface of the semiconductor substrate, and the first plurality of vias and the second plurality of vias are aligned to the vertical plane.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yu-Ling
• Yen Hsiao-Tsung
• Chen Ho-Hsiang
• Kuo Chin-Wei
• Jou Chewn-Pu

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title