Method for manufacturing semiconductor substrate

US9831086B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9831086-B2
Application numberUS-201715468900-A
CountryUS
Kind codeB2
Filing dateMar 24, 2017
Priority dateMar 30, 2016
Publication dateNov 28, 2017
Grant dateNov 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for manufacturing a semiconductor substrate that, even when a substrate which has, on a surface thereof, a three-dimensional structure having nanometer-scale microvoids on a surface thereof is used, can allow an impurity diffusion ingredient to be uniformly diffused into the substrate at the whole area thereof where the diffusion agent composition is coated, including the whole inner surfaces of the microvoids, while suppressing the occurrence of defects in the substrate. A coating film having a thickness of not more than 30 nm is formed on a surface of a substrate under such conditions that an atmosphere around the substrate has a relative humidity of not more than 40%, using a diffusion agent composition comprising an impurity diffusion ingredient and a Si compound that is hydrolyzable to produce a silanol group.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a semiconductor substrate, the method comprising: coating a diffusion agent composition on a semiconductor substrate I that is an object into which an impurity diffusion ingredient (A) is to be diffused, to form a coating film having a thickness of not more than 30 nm; and diffusing the impurity diffusion ingredient (A) in the diffusion agent composition into the semiconductor substrate I, wherein the diffusion agent composition contains the impurity diffusion ingredient (A) and a Si compound (B) that is hydrolyzable to produce a silanol group, and in coating the diffusion agent composition, an atmosphere around the semiconductor substrate I has a relative humidity of not more than 40%. 2. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the atmosphere has a temperature of not more than 23° C. 3. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the Si compound (B) is a compound represented by the following formula (1): R 4-n Si(NCO) n   (1) wherein R 1 represents a hydrocarbon group; and n is an integer of 3 or 4. 4. The method for manufacturing a semiconductor substrate according to claim 3 , wherein the coating film has a thickness of 0.2 to 10 nm. 5. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the semiconductor substrate I has a three-dimensional structure having convexes and concaves on a surface on which the diffusion agent composition is coated. 6. The method for manufacturing a semiconductor substrate according to claim 1 , further comprising rinsing the coating film with an organic solvent.

Assignees

Inventors

Classifications

  • H10P32/19Primary

    Diffusion sources · CPC title

  • between a solid phase and a liquid phase · CPC title

  • using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

  • H10P32/171Primary

    being group IV material · CPC title

  • Electricity · mapped topic

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What does patent US9831086B2 cover?
A method for manufacturing a semiconductor substrate that, even when a substrate which has, on a surface thereof, a three-dimensional structure having nanometer-scale microvoids on a surface thereof is used, can allow an impurity diffusion ingredient to be uniformly diffused into the substrate at the whole area thereof where the diffusion agent composition is coated, including the whole inner s…
Who is the assignee on this patent?
Tokyo Ohka Kogyo Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P32/19. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).