Comparison operations in memory

Patent metadata

Field	Value
Publication number	US-9830999-B2
Application number	US-201514716079-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Jun 5, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

First claim

What is claimed is:

1. An apparatus comprising:
a first group of memory cells coupled to a first access line and configured to store a first element;
a second group of memory cells coupled to a second access line and configured to store a second element;
sensing circuitry coupled to the first group of memory cells and the second group of memory cells; and
a controller coupled to the sensing circuitry and configured to use the sensing circuitry to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

2. The apparatus of claim 1 , wherein performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations comprises performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations without performing a sense line address access.

3. The apparatus of claim 2 , further comprising performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations using sensing circuitry on pitch with a number of columns of complementary sense lines corresponding to the first and second groups of memory cells.

4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.

5. The apparatus of claim 4 , wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

6. A method for comparing elements comprising:
performing, without transferring data via an input/output (I/O) line, a comparison operation on:
a first element stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and
a second element stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and

wherein the comparison operation provides a result that indicates whether the first element is equal to the second element or which of the first element and the second element is greater.

7. The method of claim 6 , further comprising storing the first element as a first bit-vector in the first group of memory cells, wherein each memory cell in the first group of memory cells stores a respective bit from the first bit-vector.

8. The method of claim 7 , further comprising storing the second element as a second bit-vector in the second group of memory cells, wherein each memory cell in the second group of memory cells stores a respective bit from the second bit-vector.

9. The method of claim 6 , wherein the first element is a first value and the second element is a second value, and wherein the result of the comparison operation indicates whether the first value is equal to the second value or which of the first value and the second value is greater.

10. An apparatus comprising:
a first group of memory cells coupled to a first access line and to a number of sense lines and configured to store a first element;
a second group of memory cells coupled to a second access line and to the number of sense lines and configured to store a second element;
a third group of memory cells configured to store a result of a comparison operation performed on the first element and the second element, the third group of cells comprising:
a number of cells coupled to a third access line and to the number of sense lines; and
a number of cells coupled to a fourth access line and to the number of sense lines;

sensing circuitry coupled to the first group of memory cells, the second group of memory cells, and the third group of memory cells; and
a controller coupled to the sensing circuitry and configured to:
use the sensing circuitry to perform the comparison operation; and
cause the result of the comparison operation to be stored in the third group of memory cells without transferring data via an input/output (I/O) line.

11. The apparatus of claim 10 , wherein the controller is further configured to cause the result of the comparison operation to be stored as:
a first bit-vector that identifies differences in the first element as compared to the second element; and
a second bit-vector that identifies differences in the second element as compared to the first element.

12. The apparatus of claim 11 , wherein the controller is further configured to use the sensing circuitry to determine a first index that identifies a most significant one (1) bit in the first bit-vector.

13. The apparatus of claim 12 , wherein the controller is further configured to use the sensing circuitry to determine a second index that identifies a most significant one (1) bit in the second bit-vector.

14. The apparatus of claim 13 , wherein the controller is further configured to cause, responsive to a determination that the first index is greater than the second index:
a particular bit-vector to be stored in the number of memory cells coupled to the third access line; and
a different particular bit-vector to be stored in the number of memory cells coupled to the fourth access line to indicate that the first element is greater than the second element.

15. The apparatus of claim 14 , wherein the controller is further configured to cause, responsive to a determination that the second index is greater than the first index:
the different particular bit-vector to be stored in the number of memory cells coupled to the third access line; and
the particular bit-vector to be stored in the number of memory cells coupled to the fourth access line to indicate that the second element is greater than the first element.

16. The apparatus of claim 14 , wherein the controller is further configured to cause, responsive to a determination that the first and second indices are the same:
the particular bit-vector to be stored in the number of memory cells coupled to the third access line; and
the particular bit-vector to be stored in the number of memory cells coupled to the fourth access line to indicate that the first element is equal to the second element.

17. A method for comparing elements comprising:
performing, without transferring data via an input/output (I/O) line, a comparison operation in memory on:
a plurality (M) of first elements stored in a first group of memory cells coupled to a first access line and to a number (C) of sense lines of a memory array; and
a plurality (M) of second elements stored in the second group of memory cells coupled to a second access line and to the C sense lines of the memory array; and

providing a comparison operation result that indicates whether the M first elements are equal to the M second elements or which of the M first elements and the M second elements are greater.

18. The method of claim 17 , wherein each of the M first elements and the M second elements are comprised of N bits.

19. The method of claim 18 , wherein M is equal to C divided by N.

20. The method of claim 18 , wherein each of the N bits in each of the M first elements and the M second elements are associated with an index and wherein bits from corresponding elements that are associated with a same index are stored in memory cells that are coupled to a same sense line from the C sense lines.

21. The method of claim 18 , further comprising, identifying a most significant bit (MSB) for the M first elements and the M second elements.

22. The method of

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C29/32

  Serial access; Scan testing · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C16/10

  Programming or data input circuits · CPC title