Neuromorphic memory circuit using a dendrite leaky integrate and fire (LIF) charge

Patent metadata

Field	Value
Publication number	US-9830982-B2
Application number	US-201514749413-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jan 14, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.

First claim

What is claimed is:

1. A method for operating a neuromorphic memory circuit, the method comprising:
accumulating a dendrite leaky integrate and fire (LIF) charge over time on a conductive dendrite LIF line;
transmitting an axon LIF pulse on a conductive axon LIF line;
switching on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse;
transmitting a dendrite spike timing dependent plasticity (STDP) pulse if voltage at the dendrite LIF line falls below a threshold voltage;
transmitting an axon STDP pulse on a conductive axon STDP line;
switching on a STDP transistor by the axon STDP pulse, the STDP transistor providing an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.

2. The method of claim 1 , further comprising determining if the voltage at the dendrite LIF line falls below a threshold voltage by a comparator electrically coupled to the conductive dendrite LIF line and the threshold voltage.

3. The method of claim 1 , further comprising:
generating the axon LIF pulse by an axon LIF pulse generator electrically coupled to the conductive axon LIF line;
generating the axon STDP pulse by an axon STDP pulse generator electrically coupled to the conductive axon STDP line; and
generating the dendrite STDP pulse by a dendrite STDP pulse generator electrically coupled to the dendrite STDP line.

4. The method of claim 1 , further comprising preventing creation of the discharge path for the dendrite LIF charge through both the LIF transistor and the STDP transistor by a collision avoidance transistor in series circuit with the STDP transistor.

5. The method of claim 4 , further comprising:
inverting the axon LIF pulse to generate an inverted axon LIF pulse; and
switching the collision avoidance transistor by the inverted axon LIF pulse such that when the LIF transistor is switched on, the collision avoidance transistor is switched off.

Assignees

• IBM

Inventors

• Kim Sangbum
• Lam Chung H

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• G11C11/54 Primary

  using elements simulating biological cells, e.g. neuron · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title