DC balancing techniques for a variable refresh rate display

US9830871B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9830871-B2
Application numberUS-201414147365-A
CountryUS
Kind codeB2
Filing dateJan 3, 2014
Priority dateJan 3, 2014
Publication dateNov 28, 2017
Grant dateNov 28, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame pattern are of a different time duration than frames of negative polarity, and wherein the frame pattern results in an accumulation of charge in pixels of the display panel. The method also comprises correcting for the charge accumulation by disrupting the frame pattern.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for driving a display panel having a variable refresh rate, said method comprising: detecting a condition that results in a charge accumulation in said display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source, wherein said DC imbalance is a result of a beat pattern comprising alternating frames of differing polarities, wherein each frame of positive polarity within said beat pattern is of a different time duration than each frame of negative polarity, and wherein said beat pattern results in an accumulation of charge in pixels of said display panel; and correcting for said charge accumulation by disrupting said beat pattern, wherein said correcting comprises one of: adjusting a refresh time of frames in said beat pattern in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern; delaying rendering of frames in said beat pattern at said image source in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern. 2. The method of claim 1 , wherein said correcting further comprises: toggling an input to said display panel, wherein said toggling switches a polarity of a frame in said beat pattern and reverses said beat pattern. 3. The method of claim 2 , wherein an external input to driving electronics for the display panel can be used to change said polarity of said frame in said beat pattern. 4. The method of claim 1 , wherein said correcting further comprises: repeating a frame in said beat pattern, wherein said repeating reverses said beat pattern. 5. The method of claim 4 , wherein a repeated frame is evenly spaced between a frame prior to said repeated frame and a frame subsequent to said repeated frame. 6. The method of claim 1 , wherein said correcting further comprises: dropping a frame in said beat pattern, wherein said dropping reverses said beat pattern. 7. The method of claim 1 , wherein said image source is a graphics processing unit (GPU). 8. The method of claim 1 , wherein said detecting further comprises: modeling said accumulation of charge to decay in response to time durations of said frames of positive polarity and said frames of negative polarity being equal. 9. A system comprising: a variable refresh rate display; a memory for storing images from an image source; a processor coupled to said memory, said processor operable to implement a method for controlling said variable refresh rate display, said method comprising: detecting a condition that results in a DC imbalance in said variable refresh rate display using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from said image source, wherein said DC imbalance is a result of a beat pattern comprising alternating frames of differing polarities, wherein each frame of positive polarity within said beat pattern is of a different time duration than each frame of negative polarity, and wherein said beat pattern results in an accumulation of charge in pixels of said variable refresh rate display; and correcting for said DC imbalance by disrupting said beat pattern, wherein said correcting comprises one of: adjusting a refresh time of frames in said beat pattern in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern; delaying rendering of frames in said beat pattern at said image source in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern. 10. The system of claim 9 , wherein said correcting further comprises: toggling an input to said variable refresh rate display, wherein said toggling switches a polarity of a frame in said beat pattern and reverses said beat pattern. 11. The system of claim 9 , wherein said correcting further comprises: repeating a frame in said beat pattern, wherein said repeating reverses said beat pattern. 12. The system of claim 11 , wherein a repeated frame is evenly spaced between a frame prior to said repeated frame and a frame subsequent to said repeated frame. 13. The system of claim 9 , wherein said correcting further comprises: dropping a frame in said beat pattern, wherein said dropping reverses said beat pattern. 14. The system of claim 9 , wherein said image source is a graphics processing unit (GPU). 15. The system of claim 9 , wherein said variable refresh rate display is a Liquid Crystal Display (LCD) panel. 16. The system of claim 9 , wherein said detecting further comprises: modeling said accumulation of charge to decay in response to time durations of said frames of positive polarity and said frames of negative polarity being equal. 17. A method for controlling a display panel with a variable refresh rate, said method comprising: determining intervals to perform DC imbalance correction in a variable refresh rate display using a pseudo-random generator, wherein said DC imbalance is a result of a beat pattern comprising alternating frames of differing polarities, wherein each frame of positive polarity within said beat pattern is of a different time duration than each frame of negative polarity, and wherein said beat pattern results in an accumulation of charge in pixels comprising said variable refresh rate display; and correcting for said DC imbalance at said intervals by disrupting said beat pattern, wherein said correcting comprises one of: adjusting a refresh time of frames in said beat pattern in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern; delaying rendering of frames in said beat pattern at said image source in order for said frames of positive polarity in said beat pattern to be equal in time duration to said frames of negative polarity in said beat pattern. 18. The method of claim 17 , wherein said correcting further comprises: toggling an input to said variable refresh rate display, wherein said toggling switches a polarity of a frame in said beat pattern and reverses said beat pattern.

Assignees

Inventors

Classifications

  • G09G3/3618Primary

    with automatic refresh of the display panel using sense/write circuits · CPC title

  • Control of polarity reversal in general · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

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What does patent US9830871B2 cover?
A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising altern…
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/3618. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).