Arithmetic processing device for disabling an unnecessary prefetch command and control method of arithmetic processing device for disabling an unnecessary prefetch command

Patent metadata

Field	Value
Publication number	US-9830268-B2
Application number	US-201514695341-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	May 14, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.

First claim

What is claimed is:

1. An arithmetic processing device comprising:
a decoder which decodes commands and outputs the decoded commands;
a command holding circuit configured to receive the outputted decoded commands and register therein a first command among the received decoded commands, the first command involving memory accesses and being executed as a software prefetch;
a hardware prefetch controller configured to execute a hardware prefetch in response to a trigger different from the first command, the hardware prefetch being an operation of transferring data stored in a memory to a cache memory; and
a controller configured to determine whether the first command registered in the command holding circuit is an unnecessary prefetch command in accordance with the hardware prefetch, and disable the determined unnecessary prefetch command.

2. The arithmetic processing device according to claim 1 , wherein
the controller is configured to disable the unnecessary prefetch command by deleting the unnecessary prefetch command from the command holding circuit.

3. The arithmetic processing device according to claim 1 , wherein
the hardware prefetch controller includes an address holding circuit configured to store therein first address information to which the hardware prefetch controller refers in order to detect the trigger different from the first command, and calculate an access destination of the prefetch based on the first address information stored in the address holding circuit,
the command holding circuit is configured to store therein a command code indicating a type of the first command, and second address information indicating an access destination of the first command, and
when the hardware prefetch controller executes the hardware prefetch, the controller determines whether the unnecessary prefetch command to access the access destination calculated based on the first address information is registered in the command holding circuit based on the command codes and the second address information which are stored in the command holding circuit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding circuit.

4. A control method of an arithmetic processing device, comprising:
decoding commands by a decoder in the arithmetic processing device;
outputting the decoded commands by the decoder;
receiving, in a command holding circuit, the outputted decoded commands;
registering, in the command holding circuit, a first command among the received decoded commands, the first command involving memory accesses and being executed as a software prefetch;
in response to a trigger different from the first command, executing the hardware prefetch by a hardware prefetch controller in the arithmetic processing device, the hardware prefetch being an operation of transferring data stored in a memory to a cache memory in advance;
determining, by a controller in the arithmetic processing device, whether the first command registered in the command holding circuit is an unnecessary prefetch command in accordance with the hardware prefetch; and
disabling the determined unnecessary prefetch command.

5. The control method according to claim 4 , wherein
the disabling of the unnecessary prefetch command by the controller is performed by deleting the unnecessary prefetch command from the command holding circuit.

6. The control method according to claim 4 , further comprising:
storing, in an address holding circuit by the hardware prefetch controller, first address information to which the hardware prefetch controller refers in order to detect the trigger different from the first command;
calculating an access destination of the hardware prefetch by the hardware prefetch controller based on the first address information stored in the address holding circuit;
storing, in the command holding circuit, a command code indicating a type of the first command, and second address information indicating an access destination of the first command, and
when the hardware prefetch controller executes the hardware prefetch, determining, by the controller, whether the unnecessary prefetch command to access the access destination calculated based on the first address information is registered in the command holding circuit based on the command codes and the second address information which are stored in the command holding circuit; and
disabling the unnecessary prefetch command by the controller, when the unnecessary prefetch command is registered in the command holding circuit.

Assignees

• Fujitsu Ltd

Inventors

• Kimura Shigeru

Classifications

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title

• G06F2212/1024

  Latency reduction · CPC title