Region descriptor management method and electronic apparatus thereof

Patent metadata

Field	Value
Publication number	US-9830261-B2
Application number	US-201514700114-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Mar 5, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the electronic apparatus and includes following steps. Region descriptor entries are fetched from a region descriptor table. Each of the region descriptor entries includes a block initial address and a block length to describe a memory block of a memory module. According to the block initial addresses and the block lengths of the region descriptor entries, a portion of the region descriptor entries are adjusted to be at least one current region descriptor entry. Based on the at least one current region descriptor entry, a current region descriptor table is generated.

First claim

What is claimed is:

1. A region descriptor management method, adapted to a device controller of an electronic apparatus, the management method comprising:
fetching a plurality of region descriptor entries from a region descriptor table, wherein each of the plurality of region descriptor entries comprises a block initial address and a block length to correspondingly describe a memory block of a memory module;
according to the block initial addresses and the block lengths of the plurality of region descriptor entries, combining and adjusting a portion of the plurality of region descriptor entries to be at least one current region descriptor entry; and
based on the at least one current region descriptor entry, generating a current region descriptor table, wherein the number of current region descriptor entries in the current region descriptor table is less than the number of region descriptor entries in the region descriptor table.

2. The region descriptor management method as claimed in claim 1 , wherein the memory blocks described by the portion of the plurality of region descriptor entries are physically continuously arranged in the memory module.

3. The region descriptor management method as claimed in claim 1 , wherein the step of adjusting the portion of the plurality of region descriptor entries to be the at least one current region descriptor entry further comprises:
by using a plurality of constant block addresses and a constant block length, comparing the block initial addresses and the block lengths of the portion of the plurality of region descriptor entries, so as to generate at least one current block initial address and at least one current block length; and
according to the at least one current block initial address and the at least one current block length, obtaining the at least one current region descriptor entry.

4. The region descriptor management method as claimed in claim 3 , wherein the current block length included in each of the at least one current region descriptor entry is not greater than the constant block length.

5. The region descriptor management method as claimed in claim 1 , further comprising:
writing the at least one current region descriptor entry into the memory module.

6. The region descriptor management method as claimed in claim 1 , further comprising:
performing a data transmission process of the at least one memory block indicated by the at least one current region descriptor entry.

7. An electronic apparatus, comprising:
a host system comprising a memory module;
a storage device; and
a device controller, coupled between the host system and the storage device,
wherein the device controller fetches a plurality of region descriptor entries from a region descriptor table of the host system, wherein each of the plurality of region descriptor entries comprises a block initial address and a block length to correspondingly describe a memory block of the memory module,
wherein according to the block initial addresses and the block lengths of the plurality of region descriptor entries, the device controller combines and adjusts a portion of the plurality of region descriptor entries to be at least one current region descriptor entry, and based on the at least one current region descriptor entry, the device controller generating a current region descriptor table, wherein the number of current region descriptor entries in the current region descriptor table is less than the number of region descriptor entries in the region descriptor table.

8. The electronic apparatus as claimed in claim 7 , wherein the memory blocks described by the portion of the plurality of region descriptor entries are physically continuously arranged in the memory module.

9. The electronic apparatus as claimed in claim 7 , wherein by using a plurality of constant block addresses and a constant block length, the device controller compares the block initial addresses and the block lengths of the portion of the plurality of region descriptor entries, so as to generate at least one current block initial address and at least one current block length, and
according to the at least one current block initial address and the at least one current block length, the device controller obtains the at least one current region descriptor entry.

10. The electronic apparatus as claimed in claim 9 , wherein the current block length included in each of the at least one current region descriptor entry is not greater than the constant block length.

11. The electronic apparatus as claimed in claim 7 , wherein the device controller writes the at least one current region descriptor entry into the memory module.

12. The electronic apparatus as claimed in claim 7 , wherein the device controller obtains a data from the at least one memory block described by the at least one current region descriptor entry and stores the data in the storage device, or the device controller obtains a data from the storage device and stores the data in the at least one memory block described by the at least one current region descriptor entry.

Assignees

• Lite On Technology Corp

Inventors

• Jiang Wei-Ling
• Lee Yi-Chung

Classifications

• G06F13/4208

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• G06F12/0623

  for memory modules · CPC title

• G06F3/0601

  Interfaces specially adapted for storage systems · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title