CPU-to-GPU and GPU-to-GPU atomics

Patent metadata

Field	Value
Publication number	US-9830210-B2
Application number	US-201314011671-A
Country	US
Kind code	B2
Filing date	Aug 27, 2013
Priority date	Mar 15, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.

First claim

What is claimed is:

1. A computer-implemented method for performing an atomic operation on a memory page shared by at least two processing units, the method comprising:
receiving a request from a first processing unit to perform an atomic operation on the memory page, wherein the memory page corresponds to a first page table entry included in a first page table associated with the first processing unit, and the first page table entry includes an atomic permission bit;
determining that the atomic permission bit in the first page table entry is inactive;
removing all page table entries that are associated with the memory page from a second page table associated with a second processing unit;
activating the atomic permission bit; and
while the atomic permission bit is active, performing the atomic operation on the memory page while denying memory write and atomic accesses to the second processing unit.

2. The method of claim 1 , further comprising generating a fault based on the value of the atomic permission bit.

3. The method of claim 2 , wherein the first page table entry corresponds to a virtual address that is associated with the memory page.

4. The method of claim 3 , further comprising updating a page state entry included in a page state directory to a state that reflects the activated atomic permission bit.

5. The method of claim 1 , further comprising:
determining that the atomic operation has completed and that another processor is attempting to access the memory page; and
inactivating the atomic permission bit.

6. The method of claim 1 , wherein activating the atomic permission bit provides the first processing unit with exclusive access to the memory page.

7. The method of claim 1 , wherein the first processing unit comprises a parallel processing unit and, the second processing unit comprises a central processing unit.

8. The method of claim 1 , wherein the first processing unit comprises a parallel processing unit, and the second processing unit comprises another parallel processing unit.

9. The method of claim 1 , further comprising performing a write operation on the memory page while the atomic permission bit is inactive and the write permission bit is active.

10. A computer-implemented method for performing an atomic operation on a memory page shared by at least two processing units, the method comprising:
receiving a request from a first processing unit to perform an atomic operation on the memory page;
determining that an atomic permission bit in a first page table entry included in a first page table associated with the first processing unit is inactive, wherein the first page table entry corresponds to a virtual address that is associated with the memory page;
generating a fault based on the value of the atomic permission bit;
removing all page table entries that are associated with the memory page from a second page table associated with the second processing unit;
activating the atomic permission bit;
updating a page state entry included in a page state directory to a state that reflects the activated atomic permission bit; and
performing the atomic operation on the memory page while denying memory write and atomic accesses to the memory page by any processing unit except the first processing unit.

11. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause a first processing unit to perform an atomic operation on a memory page shared by at least two processing units, the method comprising:
receiving a request from a first processing unit to perform an atomic operation on the memory page, wherein the memory page corresponds to a first page table entry included in a first page table associated with the first processing unit, and the first page table entry includes an atomic permission bit;
determining that the atomic permission bit in the first page table entry is inactive;
removing all page table entries that are associated with the memory page from a second page table associated with a second processing unit;
activating the atomic permission bit; and
while the atomic permission bit is active, performing the atomic operation on the memory page while denying memory accesses to the second processing unit.

12. The non-transitory computer-readable storage medium of claim 11 , further comprising generating a fault based on the value of the atomic permission bit.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the first page table entry corresponds to a virtual address that is associated with the memory page.

14. The non-transitory computer-readable storage medium of claim 13 , further comprising updating a page state entry included in a page state directory to a state that reflects the activated atomic permission bit.

15. The non-transitory computer-readable storage medium of claim 11 , further comprising:
determining that the atomic operation has completed and that another processor is attempting to access the memory page; and
inactivating the atomic permission bit.

16. The non-transitory computer-readable storage medium of claim 11 , wherein activating the atomic permission bit provides the first processing unit with exclusive access to the memory page.

17. The non-transitory computer-readable storage medium of claim 11 , wherein the first processing unit comprises a parallel processing unit and, the second processing unit comprises a central processing unit.

18. The non-transitory computer-readable storage medium of claim 11 , wherein the first processing unit comprises a parallel processing unit, and the second processing unit comprises another parallel processing unit.

19. A system configured to perform an atomic operation on a memory page shared by at least two processing units, the system comprising:
a memory management unit configured to:
receive a request from a first processing unit to perform an atomic operation on the memory page, wherein the memory page corresponds to a first page table entry included in a first page table associated with the first processing unit, and the first page table entry includes an atomic permission bit and a write permission bit,
access the atomic permission bit in the first page table entry, and
cause all page table entries that are associated with the memory page to be removed from a second page table associated with a second processing unit; and

the first processing unit configured to:
while the atomic permission bit is active, perform the atomic operation on the memory page while memory accesses are denied to a second processing unit.

20. The system of claim 19 , wherein the memory management unit is further configured to generate a fault based on a value of the atomic permission bit.

21. A computer system comprising:
a first memory comprising a plurality of memory pages;
a second memory comprising a page table that includes a plurality of page table entries, wherein each page table entry comprises an atomic permission bit that is configured to allow read operations and write operations while disallowing atomic operations;
a memory management unit configured to:
receive a request from a first processor to perform an atomic operation on a first memory page included in the plurality of memory pages,
access a first atomic permission bit in a first page table entry included in the page table, wherein the first atomic permission bit is associated with the first memory page, and
cause all page table entries th

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Mashey John
• Hairgrove Mark
• Deming James Leroy
• Buschardt Cameron
• Fahs Brian

Classifications

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06T1/60

  Memory management · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F2212/2542

  Non-uniform memory access [NUMA] architecture · CPC title