Performance scalability prediction

Patent metadata

Field	Value
Publication number	US-9829957-B2
Application number	US-201414225960-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Mar 26, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A processing device implementing performance scalability prediction is disclosed. A processing device of the disclosure includes a first counter to increment with each cycle of the processing device in which threads of the processing device are active. The processing device further includes a second counter to increment with each cycle of the processing device in which execution units of the processing device are stalled for one of the threads, and an access request from the one of the threads to memory external to the processing device is pending.

First claim

What is claimed is:

1. A processing device, comprising:
a first counter to increment with each cycle of the processing device in which at least one thread of threads of the processing device is active;
a second counter to increment with each cycle of the processing device in which both of:
execution units of the processing device are stalled for one of the threads; and
an access request, from the one of the threads for which the executions units are stalled, to memory external to the processing device is pending; and

a power controller unit (PCU) communicably coupled to the first counter and the second counter, the PCU to:
calculate a scalability factor from values of the first counter and the second counter, the scalability factor to indicate a first portion of a current workload of the processing device that is to be scalable to a frequency change at the processing device, and the scalability factor to determine a second portion of the current workload that is not to be scalable to the frequency change;
determine expected performance scores of the processing device at different frequencies based on the scalability factor; and
adjust a frequency of the processing device based on the expected performance scores of the processing device at the different frequencies.

2. The processing device of claim 1 , wherein the scalability factor is calculated by subtracting the quotient of the value of the first counter and the value of the second counter from one.

3. The processing device of claim 1 , wherein the current workload comprises instructions being executed by the processing device.

4. The processing device of claim 1 , wherein the scalability factor is used to predict a performance change due to the frequency change at the processing device.

5. The processing device of claim 1 , wherein the first counter and the second counter are part of a performance monitoring unit (PMU) of the processing device.

6. The processing device of claim 1 , wherein the PCU utilizes the scalability factor as one of multiple inputs to performance optimizations performed by the PCU to adjust the frequency of the processing device.

7. The processing device of claim 1 , wherein the processing device comprises multiple cores, each core comprising an instance of the first counter and the second counter.

8. A method, comprising:
incrementing, by a processing device, a first counter with each cycle of the processing device in which at least one thread of threads of the processing device is active; and
incrementing, by the processing device, a second counter with each cycle of the processing device in which both of:
execution units of the processing device are stalled for one of the threads; and
an access request, from the one of the threads for which the executions units are stalled, to memory external to the processing device is pending;

calculating a scalability factor from values of the first counter and the second counter, the scalability factor to indicate a first portion of a current workload of the processing device that is scalable to a frequency change at the processing device;
determining, based on the scalability factor, a second portion of the current workload that is not scalable to the frequency change;
determining expected performance scores of the processing device at different frequencies based on the scalability factor; and
adjusting a frequency of the processing device based on the expected performance scores of the processing device at the different frequencies.

9. The method of claim 8 , wherein the scalability factor is calculated by subtracting the quotient of the value of the first counter and the value of the second counter from one.

10. The method of claim 8 , wherein the scalability factor is used to predict a performance change due to adjustment of the frequency at the processing device.

11. The method of claim 10 , wherein the first counter and the second counter are part of a performance monitoring unit (PMU) of the processing device, and wherein the PCU utilizes the scalability factor as one of multiple inputs to performance optimizations performed by the PCU to adjust a frequency of the processing device.

12. The method of claim 8 , wherein the processing device comprises multiple cores, each core comprising an instance of the first counter and the second counter.

13. The method of claim 8 , wherein the current workload comprises instructions being executed by the processing device.

14. A system comprising:
a memory;
a processing device communicably coupled to the memory, the processing device comprising a plurality of cores, each of the plurality of cores comprising:
a first counter to increment with each cycle of the processing device in which at least one thread of threads of the processing device is active;
a second counter to increment with each cycle of the processing device in which both of:
execution units of the processing device are stalled for one of the threads; and
an access request, from the one of the threads for which the executions units are stalled, to memory external to the processing device is pending; and

a power controller unit (PCU) communicably coupled to the first counter and the second counter, the PCU to:
calculate a scalability factor from values of the first counter and the second counter, the scalability factor to indicate a first portion of a current workload of the processing device that is to be scalable to a frequency change at the processing device, and the scalability factor to determine a second portion of the current workload that is not to be scalable to the frequency change;
determine expected performance scores of the processing device at different frequencies based on the scalability factor; and
adjust a frequency of the processing device based on the expected performance scores of the processing device at the different frequencies.

15. The system of claim 14 , wherein the scalability factor is used to predict a performance change due to the frequency change at the processing device.

16. The system of claim 14 , wherein the first counter and the second counter are part of a performance monitoring unit (PMU) of the processing device, and wherein the PCU utilizes the scalability factor as one of multiple inputs to performance optimizations performed by the PCU to adjust the frequency of the processing device.

17. The system of claim 14 , wherein the scalability factor is calculated by subtracting the quotient of the value of the first counter and the value of the second counter from one.

18. The system of claim 14 , wherein the processing device comprises multiple cores, each core comprising an instance of the first counter and the second counter.

Assignees

• Intel Corp

Inventors

• Yasin Ahmad
• Rosenzweig Nir
• Weissmann Eliezer
• Rotem Efraim Efi

Classifications

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• Y02B60/1239

  Cross-Sectional Technologies · mapped topic

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title