Resistance correction circuit, resistance correction method, and semiconductor device

Patent metadata

Field	Value
Publication number	US-9829911-B2
Application number	US-201615007842-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Oct 31, 2012
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

First claim

What is claimed is:

1. A microcomputer formed on a semiconductor chip which is sealed with a mold resin, comprising:
an oscillator circuit generating a clock signal; and
a CPU operating based on the clock signal,
wherein the oscillator circuit comprises a resistance correction circuit including:
a first resistor whose stress-resistance value relationship is a first relationship;
a second resistor whose stress-resistance value relationship is a second relationship, a variability of a resistance value of the second resistor with stress being lower than a variability of a resistance value of the first resistor with stress;
a correction target resistor whose stress-resistance value relationship is the first relationship; and
a correction section that controls the resistance value of the correction target resistor,

wherein the correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor, and
wherein the clock signal has a frequency corresponding to the resistance value of the correction target resistor.

2. The microcomputer according to claim 1 , wherein the microcomputer includes a memory.

3. The microcomputer according to claim 2 , wherein the first relationship and the second relationship differ from each other.

4. The microcomputer according to claim 2 ,
wherein the correction target resistor is set so that the resistance value thereof is equal to a target value when the correction target resistor is subjected to a reference stress, and
wherein the first resistor is set so that the resistance value thereof is equal to the resistance value of the second resistor when the first resistor is subjected to the reference stress.

5. The microcomputer according to claim 2 ,
wherein the correction section includes:
a comparator circuit that compares the resistance value of the first resistor with the resistance value of the second resistor; and
a correction circuit that corrects, in accordance with the result of comparison by the comparator circuit, the resistance value of the first resistor until the resistance value thereof agrees with the resistance value of the second resistor, and

wherein the correction circuit corrects the resistance value of the correction target resistor by an amount corresponding to a correction amount X 1 for the resistance value of the first resistor.

6. The microcomputer according to claim 5 , further comprising:
a third resistor whose stress-resistance value relationship is the second relationship; and
a fourth resistor whose stress-resistance value relationship is the second relationship,
wherein the first resistor is coupled at one end to a first power supply and at the other end to a first node,
wherein the second resistor is coupled at one end to the first node and at the other end to a second power supply,
wherein the third resistor is coupled at one end to the first power supply and at the other end to a second node,
wherein the fourth resistor is coupled at one end to the second node and at the other end to the second power supply,
wherein the comparator circuit compares the resistance value of the first resistor with the resistance value of the second resistor by comparing the potential of the first node with the potential of the second node, and
wherein the correction circuit corrects the resistance value of the first resistor until the resistance value thereof agrees with the resistance value of the second resistor by changing the resistance value of the first resistor until the first node and the second node have the same potential.

7. The microcomputer according to claim 2 , wherein the first resistor and the second resistor are positioned so as to be subjected to the same stress as the correction target resistor.

8. The microcomputer according to claim 7 ,
wherein the correction target resistor includes a plurality of series-coupled resistive elements,
wherein the first resistor includes a plurality of series-coupled resistive elements,
wherein the second resistor includes a plurality of series-coupled resistive elements,
wherein each of the resistive elements included in the correction target resistor is a resistive element of a first type,
wherein each of the resistive elements included in the first resistor is a resistive element of the first type,
wherein each of the resistive elements included in the second resistor is a resistive element of a second type, and
wherein the first resistive elements and the second resistive elements are disposed in common-centroid layout.

9. The microcomputer according to claim 8 , wherein the first resistive elements and the second resistive elements are disposed so as to alternate with each other not only in a first direction but also in a second direction, the second direction being orthogonal to the first direction.

10. The microcomputer according to claim 8 ,
wherein the first resistive elements include a plurality of first resistor groups,
wherein the second resistive elements include a plurality of second resistor groups,
wherein the first resistor groups include two of the resistive elements of the first type aligned in a first direction,
wherein the second resistor groups include two of the resistive elements of the second type aligned in the first direction, and
wherein the first resistor groups and the second resistor groups are disposed so as to alternate with each other not only in the first direction but also in a second direction.

Assignees

• Renesas Electronics Corp

Inventors

• Yayama Kosuke
• Nakamura Takashi

Classifications

• H01L28/20

  Electricity · mapped topic

• H01C13/02

  Structural combinations of resistors · CPC title

• H01L27/0802

  Electricity · mapped topic

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03B5/24

  active element in amplifier being semiconductor device (H03B5/26 takes precedence) · CPC title