Current mirror circuit and receiver using the same

Patent metadata

Field	Value
Publication number	US-9829906-B2
Application number	US-201514669063-A
Country	US
Kind code	B2
Filing date	Mar 26, 2015
Priority date	Mar 26, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current.

First claim

What is claimed is:

1. A current mirror circuit comprising:
a first transistor and a second transistor which share a power supply; and
a drain potential mirror unit that determines a predetermined potential of a drain of the second transistor such that the predetermined potential is equal to a potential of a drain of the first transistor determined based on a reference current generated by a current source,
wherein the second transistor supplies a mirror current to a load circuit based on the predetermined potential of the drain of the second transistor and the potential of the drain of the first transistor, and
wherein a drain potential mirror unit that amplifies the reference current generated by a current source at a first magnification to generate a first current, amplifies the generated first current at a second magnification to generate a second current, and determines the predetermined potential of the drain of the second transistor based on the second current.

2. The current mirror circuit according to claim 1 , wherein the first magnification and the second magnification are designed such that the predetermined potential is equal to a potential of a drain of the first transistor.

3. The current mirror circuit according to claim 1 , wherein the drain potential mirror unit comprises:
a third transistor and a sixth transistor which share the power supply shared by the first transistor; and
a fourth transistor and a fifth transistor which have a common source potential, and
wherein the drain potential mirror unit supplies the first current from the third transistor to the fourth transistor based on a potential of a gate of the first transistor determined based on the reference current, supplies the second current from the fifth transistor to the sixth transistor based on a potential of a gate of the fourth transistor determined based on the first current, and determines, as the predetermined potential, a potential of a gate of the sixth transistor based on the second current.

4. The current mirror circuit according to claim 3 , wherein the drain potential mirror unit further comprises a seventh transistor provided between the second transistor and the load circuit.

5. The current mirror circuit according to claim 4 , wherein a potential equal to a potential of a drain of the sixth transistor is provided to a gate of the seventh transistor.

6. The current mirror circuit according to claim 3 ,
wherein the first transistor, the second transistor, the third transistor, and the sixth transistor are PMOS transistors, and
wherein the fourth transistor and the fifth transistor are NMOS transistors.

7. The current mirror circuit according to claim 3 ,
wherein the first transistor, the second transistor, the third transistor, and the sixth transistor are NMOS transistors, and
wherein the fourth transistor and the fifth transistor are PMOS transistors.

8. The current mirror circuit according to claim 1 , wherein the drain potential mirror unit further comprises a transistor provided between the second transistor and the load circuit.

9. A receiver that measures a strength of an optical signal output from a transmitter, the receiver comprising:
a photodetector that generates a reference current based on the optical signal;
a current mirror circuit that amplifies the reference current at a predetermined magnification to generate a mirror current;
a current mode AD converter that converts the mirror current to a digital voltage signal at a predetermined conversion rate; and
a logic unit that measures the strength of the optical signal indicated by the digital voltage signal,
wherein the current mirror circuit comprises:
a first transistor and a second transistor which share a power supply; and
a drain potential mirror unit that determines a predetermined potential of a drain of the second transistor such that the predetermined potential is equal to a potential of a drain of the first transistor determined based on a reference current generated by a current source,
wherein the second transistor supplies the mirror current to the current mode AD converter based on the potential of the drain of the first transistor determined based on the reference current.

10. The receiver according to claim 9 ,
wherein the drain potential mirror unit that amplifies the reference current at a first magnification to generate a first current, amplifies the generated first current at a second magnification to generate a second current, and determines a predetermined potential of a drain of the second transistor based on the second current.

11. The receiver according to claim 10 ,
wherein the first magnification and the second magnification are designed such that the predetermined potential is equal to a potential of a drain of the first transistor.

12. The receiver according to claim 10 , wherein the drain potential mirror unit comprises:
a third transistor and a sixth transistor which share the power supply shared by the first transistor; and
a fourth transistor and a fifth transistor which have a common source potential, and
wherein the drain potential mirror unit supplies the first current from the third transistor to the fourth transistor based on a potential of a gate of the first transistor determined based on the reference current, supplies the second current from the fifth transistor to the sixth transistor based on a potential of a gate of the fourth transistor determined based on the first current, and determines, as the predetermined potential, a potential of a gate of the sixth transistor based on the second current.

13. The receiver according to claim 12 ,
wherein the drain potential mirror unit further comprises a seventh transistor provided between the second transistor and the load circuit, and
wherein the drain potential mirror unit supplies a potential equal to a potential of a drain of the sixth transistor to a gate of the seventh transistor.

14. The receiver according to claim 9 , further comprising a voltage comparator that compares a first potential determined based on the reference current and a second potential based on a bias circuit to determine whether the first potential is higher than the second potential,
wherein the current mode AD converter determines the predetermined conversion rate based on the determination by the voltage comparator, and
wherein the logic unit measures the strength of the optical signal indicated by the digital voltage signal according to the determination by the voltage comparator.

15. The receiver according to claim 14 , wherein the current mode AD converter comprises:
a variable resistance with a resistance value determined based on the determination by the voltage comparator, the variable resistance converting the mirror current to an analog voltage signal at a voltage drop according to the mirror current; and
an AD converter that converts the analog voltage signal to the digital voltage signal.

16. The receiver according to claim 14 , wherein the current mode AD converter sets the predetermined conversion rate to a first value if the voltage comparator determines that the first potential is higher than the second potential and sets the predetermined conversion rate to a second value not higher than the first value if the voltage comparator determines that the first potential is not higher than the second potential.

17. The receiver according to claim 14 , wherein the voltage comparator generates a comparison signal with a potential determined based on the determination, and determines the second potential base

Assignees

• Megachips Corp

Inventors

• Yamahana Ryota

Classifications

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H03G3/3084

  in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves (H03G3/32, H03G3/34 take precedence) · CPC title

• H03F3/50

  Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower · CPC title

• H03F2200/474

  A current mirror being used as sensor · CPC title

• H04B10/60

  Receivers · CPC title