Radio communication device and semiconductor integrated circuit device used for the same

Patent metadata

Field	Value
Publication number	US-9826538-B2
Application number	US-201514869753-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Jan 27, 2005
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.

First claim

What is claimed is:

1. A semiconductor device comprising a first controller,
wherein the first controller includes:
a first circuitry configured to select one frequency channel from a plurality of frequency channels,
a reception circuitry configured to receive packet data via the selected frequency channel, and count the number of operations to receive the packet data via the selected frequency channel;
an error detection circuitry configured to detect a packet synchronization error and a synchronization detection error at the selected frequency channel, and to sum up the number of packet synchronization errors and the number of synchronization detection errors,
a second controller configured to calculate a packet error rate for the selected frequency channels based on the number obtained by summing the number of packet synchronization errors and the number of synchronization detection errors, and the number of operations; and
a transmission circuitry configured to transmit packet data by using the selected frequency channel.

2. The device according to claim 1 ,
wherein the second controller is configured to control selection operation of the first circuitry based on the packet error rate.

3. The device according to claim 2 ,
wherein the second controller is configured to
determine whether a frequency channel is usable or not based on the result of evaluation of the packet error rate, and
control selection operation of the first circuitry to avoid a frequency channel which is determined as unusable.

4. The device according to claim 2 ,
wherein after the second controller has calculated the packet error rate, the error detection circuitry is configured to reset the number of operations to receive the packet data and the synchronization detection errors.

5. The device according to claim 2 ,
wherein if the number of operations is lower than a predetermined number, the second controller is configured to not calculate the packet error rate, and the error detection circuitry is configured to not reset the number of operations to receive the packet data and the synchronization detection errors.

6. The device according to claim 2 ,
wherein the synchronization detection error indicates that a Sync Word of a preset pattern be not able to detect within a predetermined time period.

7. The device according to claim 6 ,
wherein the packet synchronization error is a header error or a data section error.

8. The device according to claim 7 ,
wherein the header error indicates that an error is detected in header error inspection, and the detected error exceeds ability of an error correction code, and
the data section error indicates that an error is detected in data section error inspection, and the detected error exceeds the ability of the error correction code.

9. A semiconductor device comprising a controller,
wherein the controller is configured to
select one frequency channel from a plurality of frequency channels,
receive packet data via the selected frequency channel,
count the number of operations to receive the packet data via the selected frequency channel,
detect a packet synchronization error and a synchronization detection error at the selected frequency channel,
sum up the number of packet synchronization errors and the number of synchronization detection errors,
calculate a packet error rate for the selected frequency channels based on the number obtained by summing the number of packet synchronization errors and the number of synchronization detection errors, and the number of operations, and
transmit packet data by using the selected frequency channel.

10. The device according to claim 9 ,
wherein the controller is configured to
determine whether each frequency channel is usable or not based on the packet error rate, and
select one frequency channel to avoid frequency channels which are determined as unusable.

11. The device according to claim 10 ,
wherein after the selection of the frequency channel, the controller is configured to reset the number of operations to receive the packet data and the synchronization detection errors.

12. The device according to claim 11 ,
wherein if the number of operations is lower than a predetermined number, the controller is configured to not calculate the packet error rate, and to not reset the number of operations to receive the packet data and the synchronization detection errors.

13. The device according to claim 9 ,
wherein the synchronization detection error indicates that a Sync Word of a preset pattern be not able to detect within a predetermined time period.

14. The device according to claim 13 ,
wherein the packet synchronization error is a header error or a data section error.

15. The device according to claim 14 ,
wherein the header error indicates that an error is detected in header error inspection, and the detected error exceeds ability of an error correction code, and
the data section error indicates that an error is detected in data section error inspection, and the detected error exceeds the ability of the error correction code.

Assignees

• Toshiba Kk

Inventors

• Kizu Toshiki
• Shimojo Yoshimitsu
• Shigeta Yoshinori
• Shobatake Yasuro

Classifications

• H04W72/542 Primary

  using measured or perceived quality · CPC title

• H04W72/0453

  Resources in frequency domain, e.g. a carrier in FDMA · CPC title

• H04B1/715 Primary

  Interference-related aspects · CPC title

• H04B1/713

  using frequency hopping · CPC title

• H04B1/7136

  Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform · CPC title