Low distortion single-to-differential wide-band variable gain amplifier for optical communications

Patent metadata

Field	Value
Publication number	US-9826291-B2
Application number	US-201514879598-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Oct 9, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a single-to-differential variable gain amplifier having a variable resistor switch that substantially always operates in a triode region at all time. Said another way, the resistor switch is configured to operate in a triode region regardless of whether or not a first portion of an input signal to the variable gain amplifier is larger than a second portion of the input signal. The disclosed scheme helps to keep the variable resistor switch in the triode region in all cases of operation, thereby maintaining the linearity condition and reducing distortion in the variable gain amplifier.

First claim

What is claimed is:

1. An amplifier, comprising:
a first switch receiving a first portion of an input signal received at the amplifier;
a second switch receiving a second portion of the input signal;
an N-type Metal-Oxide-Semiconductor (NMOS) resistor switch connected between the first and second switches, wherein the NMOS resistor switch is configured to operate in a triode region regardless of whether or not the first portion of the input signal is larger than the second portion of the input signal; and
a Direct Current (DC)-blocking capacitor connected between a base of the first switch and a gate of the NMOS resistor switch that blocks a common-mode bias voltage on the first switch from reaching a gate voltage of the NMOS resistor switch.

2. The amplifier of claim 1 , wherein the first switch comprises a first transistor having the base, a collector, and an emitter and wherein the second switch comprises a second transistor having a base, a collector, and an emitter.

3. The amplifier of claim 2 , wherein the DC-blocking capacitor causes the gate of the NMOS resistor switch to track the input signal by maintaining the NMOS resistor switch in the triode region.

4. The amplifier of claim 3 , wherein the half-wave rectifier along with the DC-blocking capacitor allow only a positive signal blocking in both a common mode voltage and a negative signal from reaching the gate of the NMOS resistor switch.

5. The amplifier of claim 2 , further comprising:
a half-wave rectifier connected between the DC-blocking capacitor and the base of the first transistor.

6. The amplifier of claim 2 , wherein the DC-blocking capacitor causes the NMOS resistor switch to remain in the triode region when a base voltage of the first transistor is greater than a base voltage of the second transistor.

7. The amplifier of claim 1 , wherein the NMOS resistor switch is connected across a pair of resistors that connect an emitter of the first switch with an emitter of the second switch.

8. The amplifier of claim 1 , wherein the input signal comprises a Pulse Amplitude Modulated (PAM) signal.

9. The amplifier of claim 1 , wherein the input signal is received from a photodiode.

10. The amplifier of claim 1 , wherein the input signal is transmitted using a modulation technique that doubles an achievable data rate for a given link bandwidth.

11. The amplifier of claim 1 , wherein an NMOS resistance is controlled by an independent bias voltage on the gate of the NMOS resistor switch.

12. The amplifier of claim 1 , wherein a maximum distortion in the amplifier is maintained below a threshold value of four percent.

13. A circuit, comprising:
a photodiode configured to receive an optical signal and convert the optical signal into an electrical signal; and
one or more variable gain amplifiers configured to receive the electrical signal or a variant thereof and amplify the received electrical signal or the variant thereof, wherein each of the one or more variable gain amplifiers comprise:
a first transistor;
a second transistor; and
an N-type Metal-Oxide-Semiconductor (NMOS) resistor switch connected between the first and second transistors, wherein the NMOS resistor switch is configured to operate in a triode region when an input voltage at a base of the first switch is greater than an input voltage at a base of the second switch, wherein the NMOS resistor switch is also configured to operate in the triode region when the input voltage at the base of the first switch is less than the input voltage at the base of the second switch, and wherein at least one of the one or more variable gain amplifiers comprise a Direct Current (DC)-blocking capacitor connected between a base of the first transistor and a gate of the NMOS resistor switch thereby blocking a common-mode bias voltage on the first switch from reaching a gate voltage of the NMOS resistor switch.

14. The circuit of claim 13 , wherein the DC-blocking capacitor causes the gate of the NMOS resistor switch to track the electrical signal received at the one or more variable gain amplifiers by maintaining the NMOS resistor switch in the triode region.

15. The circuit of claim 13 , wherein the at least one of the one or more variable gain amplifiers further comprises a half-wave rectifier.

16. The circuit of claim 15 , wherein the half-wave rectifier is connected between the DC-blocking capacitor and the base of the first transistor.

17. The circuit of claim 16 , wherein the half-wave rectifier along with the DC-blocking capacitor allow only a positive signal blocking in both a common mode voltage and a negative signal from reaching the gate of the NMOS resistor switch.

18. The circuit of claim 17 , wherein the DC-blocking capacitor causes the NMOS resistor switch to remain in the triode region when a base voltage of the first transistor is greater than a base voltage of the second transistor.

19. An optical communication system, comprising:
an analog front end comprising one or more variable gain amplifiers, the one or more variable gain amplifiers comprising:
a first transistor;
a second transistor; and
an N-type Metal-Oxide-Semiconductor (NMOS) resistor switch connected between the first and second transistors, wherein the NMOS resistor switch is configured to operate in a triode region when an input voltage at a base of the first switch is greater than an input voltage at a base of the second switch, wherein the NMOS resistor switch is also configured to operate in the triode region when the input voltage at the base of the first switch is less than the input voltage at the base of the second switch, and wherein at least one of the one or more variable gain amplifiers comprise a Direct Current (DC)-blocking capacitor connected between a base of the first transistor and a gate of the NMOS resistor switch thereby blocking a common-mode bias voltage on the first switch from reaching a gate voltage of the NMOS resistor switch.

20. The optical communication system of claim 19 , wherein the at least one of the one or more variable gain amplifiers further comprises a half-wave rectifier connected between the DC-blocking capacitor and the base of the first transistor.

Assignees

• Avago Technologies General Ip

Inventors

• Shringarpure Rahul
• Nallani Chakravartula
• Asmanis Georgios
• Chaahoub Faouzi

Classifications

• H03F1/0205 Primary

  in transistor amplifiers · CPC title

• H04Q11/0005 Primary

  Switch and router aspects · CPC title

• H03F3/08

  controlled by light · CPC title

• H03F2200/324

  An amplitude modulator or demodulator being used in the amplifier circuit · CPC title

• H04Q2011/0013

  using gating amplifiers · CPC title