High throughput VLSI architecture for HEVC SAO encoding

Patent metadata

Field	Value
Publication number	US-9826240-B2
Application number	US-201414320712-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 5, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

An apparatus for sample adaptive offset (SAO) filtering in video encoding. A unified processing engine collects statistics on a block of pixels, determines a minimum RD cost (J) for each category of band offsets and edge offsets; determines a RD cost to find the optimal SAO type and determines a cost for each of the left SAO parameters and the up SAO parameters. The unified processing engine operates for three iterations: once for luminance once for each chrominance. A SAO merge decision unit determines an optimal mode and generates current LCU Parameters. The RD offset unit determination includes determining whether the sign of the minimum offset is proper for the category of edge offset. The RD offset is determined using a programmable look-up table indexed by the offset to estimate a rate. The unified processing engine operates on a three stage pipeline: loading blocks; processing; and updating blocks.

First claim

What is claimed is:

1. An apparatus for sample adaptive offset (SAO) filtering in video encoding comprising:
a unified processing engine including:
a statistics collection module implemented by a programmed central processing unit receiving blocks of original pixels and corresponding blocks of encoded/decoded pixels, said statistics collection module including
a subtracter forming a difference between a video attribute of each original pixel and the corresponding encoded/decoded pixel,
a plurality of band offset classifiers determining whether a pixel has a corresponding band offset,
a band offset error accumulator accumulating said difference for each pixel having a determined band offset and determining a number of pixels in a block having each band offset classification,
a plurality of edge offset classifiers determining an edge offset type for each pixel, and
an edge offset error accumulator accumulating said difference for each pixel having a determined edge offset and determining a number of pixels in a block having each edge offset classification;
a RD offset module implemented by a programmed central processing unit connected to said statistics collection module receiving said difference for each pixel having a determined band offset, said number of pixels in a block having each band offset classification from said band offset error accumulator, said difference for each pixel having a determined edge offset and said number of pixels in a block having each edge offset classification from said edge offset error accumulator, said RD offset module generating a minimum RD cost (J) for each category of band offsets and edge offsets for all possible ranges of offsets within each category as follows:
J =( NO 2 −2 OE )+λ R

where: J is the RD cost; N is the number of pixels; O is the corresponding offset value for that category; and E is difference between the original pixel and the corresponding encoded/decoded pixel; R is the bit rate after deblocking; and λ is a scaling constant, said RD offset module includes a look-up table having a plurality of entries, each entry indexed by offset and storing an estimate of R, and said RD offset module is operable to calculate J=(NO 2 −2OE)+λR employing an estimate of R from the look-up table;
a RDO for SAO type module implemented by a programmed central processing unit connected to said statistics collection module receiving said difference for each pixel having a determined band offset, said number of pixels in a block having each band offset classification from said band offset error accumulator, said difference for each pixel having a determined edge offset and said number of pixels in a block having each edge offset classification from said edge offset error accumulator and to said RD offset module receiving said minimum RD cost (J) for each category of band offsets and edge offsets, said RDO for SAO type module generating an RD cost to find the optimal SAO type as follows:
J t =J SAO −J 0 =D t +λR t

where: J t is the RD cost to find the optimal SAO type; D t is the distortion reduction by SAO; and R t is the bitrate to code the SAO parameter; and
a merge mode cost module implemented by a programmed central processing unit connected to said statistics collection module receiving said difference for each pixel having a determined band offset, said number of pixels in a block having each band offset classification from said band offset error accumulator, said difference for each pixel having a determined edge offset and said number of pixels in a block having each edge offset classification from said edge offset error accumulator and receiving left SAO parameters and up SAO parameters, said merge mode cost module determining a cost for each of the left SAO parameters and the up SAO parameters;

said unified processing engine operating once for a luminance video attribute and once for each of two chrominance video attributes; and
a SAO merge decision module implemented by a programmed central processing unit connected to said unified processing engine receiving said RD cost to find the optimal SAO type for each video attribute from said RDO for SAO type module and said cost for each of the left SAO parameters and the up SAO parameters from said merge mode cost module for each video attribute, said SAO merge decision module determining an optimal mode and generating current LCU Parameters corresponding to said optimal mode.

2. The apparatus of claim 1 , wherein:
said a statistics collection module does not test outputs of said plurality of edge offset classifiers to determine whether a current block of pixels crosses a slice boundary.

3. The apparatus of claim 1 , wherein:
said a statistics collection module does not test outputs of said plurality of edge offset classifiers to determine whether a current block of pixels crosses a tile boundary.

4. The apparatus of claim 1 , further comprising:
a SAO decoder;
a first memory storing said left SAO parameters;
a second memory storing said up SAO parameters;
wherein said unified processing engine is operable to read said left SAO parameters from said first memory and said up SAO parameters from said second memory; and
wherein said SAO decoder is operable to read said left SAO parameters from said first memory, write said left SAO parameters to said first memory, read said up SAO parameters from said second memory and write said up SAO parameters to said second memory.

5. The apparatus of claim 1 , wherein:
said RD offset module is operable to determine an offset from among said RD cost (J) for each category edge offsets having a minimum RD cost including checking whether the sign of the determined minimum offset is proper for the category of edge offset.

6. The apparatus of claim 1 , wherein:
said RD offset module determines whether the sign of the determined minimum offset is positive for categories 1 and 2 of edge offset, is negative for categories 3 and 4 of edge offset and is zero for other categories.

7. The apparatus of claim 1 , wherein:
said entries of said look-up table are programmable.

8. The apparatus of claim 1 , wherein:
said blocks of original pixels and said corresponding blocks of encoded/decoded pixels consist of 4 by 4 pixels.

9. The apparatus of claim 8 , wherein:
said unified processing engine operates on a three stage pipeline having a first stage for loading said blocks of original pixels and said corresponding blocks of encoded/decoded pixels, a second stage for processing and a third stages for updating said blocks of original pixels and said corresponding blocks of encoded/decoded pixels.

10. An apparatus for sample adaptive offset (SAO) filtering in video encoding comprising:
a unified processing engine including:
a statistics collection module implemented by a programmed central processing unit receiving blocks of original pixels and corresponding blocks of encoded/decoded pixels, said statistics collection module including
a subtracter forming a difference between a video attribute of each original pixel and the corresponding encoded/decoded pixel,
a plurality of band offset classifiers determining whether a pixel has a corresponding band offset,
a band offset error accumulator accumulating said difference for each pixel having a determined band offset and determining a number of pixels in a block having each band offset classification,
a plurality of edge offset classifiers determining an edge offset type for each pixel, and
an edge offset error accumulator accumulating said difference for each pixel having a determined edge offset and determining a number of pixels in a block having each edge offset classification;
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Assignees

• Texas Instruments Inc

Inventors

• Mody Mihir Narendra
• Garud Hrushikesh Tukaram
• Nagori Soyeb

Classifications

• H04N19/119

  Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks · CPC title

• H04N19/132

  Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking · CPC title

• H04N19/82

  involving filtering within a prediction loop · CPC title

• H04N19/117

  Filters, e.g. for pre-processing or post-processing (sub-band filter banks H04N19/635) · CPC title

• H04N19/176 Primary

  the region being a block, e.g. a macroblock · CPC title