Logarithmic pixels with correlated double sampling

Patent metadata

Field	Value
Publication number	US-9826178-B2
Application number	US-201615174506-A
Country	US
Kind code	B2
Filing date	Jun 6, 2016
Priority date	Feb 22, 2016
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

An imaging pixel may be operated in either a linear mode or a logarithmic mode. In the logarithmic mode, the voltage at a floating diffusion region may be proportional to the logarithm of the intensity of incident light. In order to enable correlated double sampling (CDS) in the logarithmic mode, a transistor may be provided that couples the photodiode to a bias voltage. When the transistor is turned off, the photodiode may be able to operate in a logarithmic mode. When the transistor is turned on, the floating diffusion region may be reset to a baseline voltage level. Images from the linear mode and the logarithmic mode may be combined to form high dynamic range images with flicker mitigation.

First claim

What is claimed is:

1. A method of operating an imaging pixel, wherein the imaging pixel comprises a photodiode, an anti-blooming transistor coupled between the photodiode and a first bias voltage, a transfer transistor coupled between the photodiode and a floating diffusion region, and a control transistor coupled between the floating diffusion region and a second bias voltage, the method comprising:
disabling the anti-blooming transistor;
asserting the transfer transistor;
asserting the control transistor;
after disabling the anti-blooming transistor and asserting the control transistor, sampling a first voltage level at the floating diffusion region, wherein sampling the first voltage level comprises sampling the first voltage level while the anti-blooming transistor is disabled, the control transistor is asserted, and the transfer transistor is asserted;
after sampling the first voltage level at the floating diffusion region, asserting the anti-blooming transistor; and
after asserting the anti-blooming transistor, sampling a second voltage level at the floating diffusion region, wherein sampling the second voltage level at the floating diffusion region comprises sampling the second voltage level while the anti-blooming transistor is asserted, the control transistor is asserted, and the transfer transistor is asserted.

2. The method defined in claim 1 , wherein asserting the anti-blooming transistor results in charge generated in the photodiode flowing through the anti-blooming transistor and exiting the imaging pixel.

3. The method defined in claim 1 , wherein disabling the anti-blooming transistor, asserting the control transistor, and asserting the transfer transistor results in the floating diffusion region having a logarithmic response to incident light.

4. The method defined in claim 1 , wherein disabling the anti-blooming transistor, asserting the control transistor, and asserting the transfer transistor results in a photocurrent flowing through the control and transfer transistors.

5. The method defined in claim 1 , further comprising:
with processing circuitry, subtracting the sample of the second voltage level from the sample of the first voltage level.

6. The method defined in claim 1 , wherein operating the imaging pixel comprises operating the imaging pixel in a logarithmic mode.

7. A method of operating an imaging pixel in a logarithmic mode, wherein the imaging pixel comprises a photodiode, a floating diffusion region, an anti-blooming transistor coupled between the photodiode and a first bias voltage, a transfer transistor coupled between the photodiode and the floating diffusion region, and a control transistor coupled between the floating diffusion region and a second bias voltage, the method comprising:
sampling a first voltage level at the floating diffusion region while the anti-blooming transistor is disabled, the transfer transistor is asserted, and the control transistor is asserted; and
sampling a second voltage level at the floating diffusion region while the anti-blooming transistor is asserted, the transfer transistor is asserted, and the control transistor is asserted.

8. The method defined in claim 7 , the method further comprising:
with processing circuitry, subtracting the sample of the second voltage level from the sample of the first voltage level.

9. The method defined in claim 7 , wherein a gate of the control transistor receives the second bias voltage when the control transistor is asserted.

10. A method of operating an imaging pixel with a photodiode, a floating diffusion region, an anti-blooming transistor coupled between the photodiode and a first bias voltage, a transfer transistor coupled between the photodiode and the floating diffusion region, and a control transistor coupled between the floating diffusion region and a second bias voltage, the method comprising:
capturing a first image using correlated double sampling while the imaging pixel operates in a linear mode, wherein capturing the first image using correlated double sampling while the imaging pixel operates in the linear mode comprises:
disabling the control transistor;
asserting the anti-blooming transistor to reset the photodiode and begin an integration time;
while the transfer transistor is disabled, asserting the control transistor to reset the floating diffusion region to a first voltage;
sampling the first voltage while the transfer transistor, anti-blooming transistor, and control transistors are disabled;
asserting the transfer transistor to end the integration time and transfer charge from the photodiode to the floating diffusion region;
after asserting the transfer transistor to end the integration time and transfer charge from the photodiode to the floating diffusion region, sampling a second voltage while the transfer transistor, anti-blooming transistor, and control transistors are disabled; and
with processing circuitry, subtracting the sample of the first voltage level from the sample of the first second level; and

capturing a second image using correlated double sampling while the imaging pixel operates in a logarithmic mode, wherein capturing the second image using correlated double sampling while the imaging pixel operates in the logarithmic mode comprises:
sampling a third voltage level at the floating diffusion region while the anti-blooming transistor is disabled, the transfer transistor is asserted, and the control transistor is asserted;
sampling a fourth voltage level at the floating diffusion region while the anti-blooming transistor is asserted, the transfer transistor is asserted, and the control transistor is asserted; and
with the processing circuitry, subtracting the sample of the fourth voltage level from the sample of the third voltage level.

11. The method defined in claim 10 , further comprising:
using the first and second captured images to form a high dynamic range image with flicker mitigation.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Beck Jeffery

Classifications

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/573 Primary

  the logarithmic type · CPC title

• H04N25/622

  by controlling anti-blooming drains · CPC title

• H04N25/617

  for reducing electromagnetic interference, e.g. clocking noise · CPC title

• H04N5/365

  Electricity · mapped topic