Adaptive bias tuning

Patent metadata

Field	Value
Publication number	US-9825788-B2
Application number	US-201615173585-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Jun 3, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

The present disclosure relates in general to devices, systems and methods for wireless communication, and in particular to communication using a proximity integrated circuit card (PICC). Example embodiments include a circuit ( 100 ) for a PICC, the circuit comprising an input stage ( 101 ), a decoding module ( 106 ) and a bias adjustment module ( 117 ), the bias adjustment module ( 117 ) configured to receive an output code from the decoding module and provide a bias adjustment signal to the input stage ( 101 ), the bias adjustment module ( 117 ) configured to iteratively tune the bias adjustment signal based on a measurement of the output code, with successive steps tuning the bias adjustment signal by a smaller amount until the output code is within a decoding range.

First claim

The invention claimed is:

1. A circuit for a proximity integrated circuit card, the circuit comprising:
an input stage having a first input for connection to a radio antenna to receive an input signal, a second input for adjustment of a bias of the input stage and an output for providing a bias adjusted input signal;
a decoding module connected to the input stage and configured to provide an output code from the bias adjusted input signal; and
a bias adjustment module connected to receive the output code from the decoding module and configured to provide a bias adjustment signal to the second input of the input stage, the bias adjustment module having a resolution of M bits, where M is an integer, and the bias adjustment module is configured to initially set the bias adjustment signal at a value corresponding to 2 M-1 ,
wherein the bias adjustment module is configured to iteratively tune the bias adjustment signal based on a measurement of the output code, with successive steps tuning the bias adjustment signal by a smaller amount until the output code is within a decoding range.

2. The circuit of claim 1 wherein, with the decoding module having an output resolution of N bits, where N is an integer, the decoding range includes an output of 2 N-1 .

3. The circuit of claim 1 wherein the bias adjustment module is configured to increase or decrease the bias adjustment signal by a value corresponding to 2 m-2 after initially setting m to be equal to M and to reduce the value of m after each iteration step.

4. The circuit of claim 3 wherein the bias adjustment module is configured to adjust the bias adjustment signal in a first direction when the output code is above the decoding range and to adjust the bias adjustment signal in a second opposing direction when the output code is below the decoding range.

5. The circuit of claim 3 , wherein the bias adjustment module is configured to stop tuning the bias adjustment signal when the output code is within the decoding range or when the value of m reaches one.

6. The circuit of claim 1 , wherein the decoding module comprises a successive approximation register analog to digital converter.

7. The circuit of claim 1 , wherein the decoding module is configured to decode an amplitude shift keyed input signal.

8. A proximity integrated circuit card comprising:
the circuit according to claim 1 ; and
an antenna connected to the input stage of the circuit.

9. A circuit for a proximity integrated circuit card, the circuit comprising:
an input stage having a first input for connection to a radio antenna to receive an input signal, wherein the first input signal is a differential signal, a second input for adjustment of a bias of the input stage and an output for providing a bias adjusted input signal, the bias adjusted input signal being a single-ended signal;
a decoding module connected to the input stage and configured to provide an output code from the bias adjusted input signal, wherein the decoding module includes current mirrors and an analog to digital converter, and wherein the decoding module is configured to convert the bias adjusted input signal to a differential signal and to provide the differential signal to the analog to digital converter; and
a bias adjustment module connected to receive the output code from the decoding module and configured to provide a bias adjustment signal to the second input of the input stage,
wherein the bias adjustment module is configured to iteratively tune the bias adjustment signal based on a measurement of the output code, with successive steps tuning the bias adjustment signal by a smaller amount until the output code is within a decoding range.

10. The circuit of claim 9 wherein, with the decoding module having an output resolution of N bits, where N is an integer, the decoding range includes an output of 2 N-1 .

11. The circuit of claim 9 wherein, with the bias adjustment module having a resolution of M bits, where M is an integer, the bias adjustment module is configured to initially set the bias adjustment signal at a value corresponding to 2 M-1 .

12. The circuit of claim 11 wherein the bias adjustment module is configured to increase or decrease the bias adjustment signal by a value corresponding to 2 m-2 after initially setting m to be equal to M and to reduce the value of m after each iteration step.

13. The circuit of claim 12 wherein the bias adjustment module is configured to adjust the bias adjustment signal in a first direction when the output code is above the decoding range and to adjust the bias adjustment signal in a second opposing direction when the output code is below the decoding range.

14. The circuit of claim 12 , wherein the bias adjustment module is configured to stop tuning the bias adjustment signal when the output code is within the decoding range or when the value of m reaches one.

15. The circuit of claim 9 , wherein the decoding module comprises a successive approximation register analog to digital converter.

16. The circuit of claim 9 , wherein the decoding module is configured to decode an amplitude shift keyed input signal.

17. A proximity integrated circuit card comprising:
the circuit according to claim 9 ; and
an antenna connected to the input stage of the circuit.

Assignees

• Nxp Bv

Inventors

• Van De Beek Remco Cornelis Herman
• Zhang Liang
• Feng Lisong
• Li Juhui
• Chang Alan

Classifications

• G06K19/0723 Primary

  the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title

• H03D1/18

  of semiconductor devices · CPC title

• G06K19/07749

  the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card · CPC title

• G06K17/0022 Primary

  arrangements or provisions for transferring data to distant stations, e.g. from a sensing device ("transfer between computer elements G06F13/00 "; data-transmission H04L) · CPC title