Independent UART BRK detection

Patent metadata

Field	Value
Publication number	US-9825754-B2
Application number	US-201615188263-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Jun 22, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.

First claim

What is claimed is:

1. A universal asynchronous receiver/transmitter (UART) module comprising:
a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a break (BRK) detection signal if the counter reaches a programmable threshold value;
wherein the counter stops counting for triggering the BRK detection signal upon a rising edge of the data signal.

2. The UART according to claim 1 , wherein the threshold value can be programmed to be 11.

3. The UART according to claim 1 , wherein the receiver unit comprises a state machine to control the counter.

4. The UART according to claim 3 , wherein the state machine is programmable to operate in different operating modes.

5. The UART according to claim 3 , further comprising a first in first out buffer memory receiving a plurality sampled data.

6. The UART according to claim 1 , wherein the programmable receiver clock is coupled to a baud rate generator.

7. A microprocessor comprising:
a universal asynchronous receiver/transmitter (UART) module comprising a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a break (BRK) detection signal if the counter reaches a programmable threshold value;
wherein the counter stops counting for triggering the BRK detection signal upon a rising edge of the data signal.

8. The microprocessor according to claim 7 , wherein the threshold value can be programmed to be 11.

9. The microprocessor according to claim 7 , wherein the receiver unit comprises a state machine to control the counter.

10. The microprocessor according to claim 9 , wherein the state machine is programmable to operate in different operating modes.

11. The microprocessor according to claim 9 , further comprising a first in first out buffer memory receiving a plurality sampled data.

12. The microprocessor according to claim 7 , wherein the programmable receiver clock is coupled to a baud rate generator.

13. A method for controlling a universal asynchronous receiver/transmitter (UART) module, the method comprising:
clocking a receiver unit by a programmable receiver clock configured to sample an incoming data signal;
resetting a counter clocked by said programmable receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal;
triggering a break (BRK) detection signal if the counter reaches a programmable threshold value; and
ceasing counting for triggering the BRK detection signal upon a rising edge of the data signal.

14. The method according to claim 13 , wherein the threshold value can be programmed to be 11.

15. The method according to claim 13 , wherein the receiver unit comprises a state machine to control the counter.

16. The method according to claim 15 , wherein the state machine is programmable to operate in different operating modes.

17. The method according to claim 15 , further comprising transmitting a plurality of sampled data to a first in first out buffer memory.

Assignees

• Microchip Tech Inc

Inventors

• Samuel Roshan

Classifications

• H04L69/28

  Timers or timing mechanisms used in protocols · CPC title

• H04L41/0681

  Configuration of triggering conditions · CPC title

• H04L43/16

  Threshold monitoring · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• H04L7/0012 Primary

  by comparing receiver clock with transmitter clock · CPC title