Transistor that employs collective magnetic effects thereby providing improved energy efficiency

Patent metadata

Field	Value
Publication number	US-9825218-B2
Application number	US-201514881372-A
Country	US
Kind code	B2
Filing date	Oct 13, 2015
Priority date	Oct 13, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits. Furthermore, the easy-in-plane magnetic films may be subdivided into regions coupled through exchange interactions and the in-plane fixed magnetic layers in the input magnetic stacks can be used in non-volatile logic and memory.

First claim

The invention claimed is:

1. A transistor, comprising:
an easy-plane ferromagnetic film with an orientation along an easy axis within a plane of a ferromagnet driven by vertical charge transport through a first and a second metal stack;
said first metal stack comprising a first non-magnetic layer directly contacting an upper surface of said easy-plane ferromagnetic film and a second non-magnetic layer directly contacting a lower surface of said easy-plane ferromagnetic film, wherein said first metal stack further comprises a first and a second ferromagnetic layer on an outside of said first and second non-magnetic layers;
said second metal stack comprising a third non-magnetic layer directly contacting said upper surface of said easy-plane ferromagnetic film and a fourth non-magnetic layer directly contacting said lower surface of said easy-plane ferromagnetic film, wherein said second metal stack further comprises a third and a fourth ferromagnetic layer with perpendicular anisotropy on an outside of said third and fourth non-magnetic layers;
input terminals connected to said first and second ferromagnetic layers of said first metal stack; and
output terminals connected to said third and fourth ferromagnetic layers of said second metal stack.

2. The transistor as recited in claim 1 , wherein in response to exceeding a critical current, said easy-plane ferromagnetic film produces an oscillatory precession about an out-of-plane axis by driving a current through said first and second metal stacks thereby increasing interlayer resistance of said first and second metal stacks and reducing current flow through said first and second metal stacks, wherein said critical current corresponds to a conserved quantity with respect to a sum of current flows through an upper output terminal and an upper input terminal in response to said first and third ferromagnetic layers of said first and second metal stacks, respectively, having a same magnetic orientation, or corresponds to a conserved quantity with respect to a sum of current flows through the upper output terminal and a lower input terminal in response to said first and third ferromagnetic layers of said first and second metal stacks, respectively, having a different magnetic orientation.

3. The transistor as recited in claim 1 , wherein said first and second ferromagnetic layers have opposite magnetic orientations, wherein said third and fourth ferromagnetic layers have opposite magnetic orientations.

4. The transistor as recited in claim 1 , wherein said first ferromagnetic layer and said third ferromagnetic layer have a same magnetic orientation, wherein said second ferromagnetic layer and said fourth ferromagnetic layer have the same magnetic orientation.

5. The transistor as recited in claim 1 , wherein said first ferromagnetic layer and said third ferromagnetic layer have a different magnetic orientation, wherein said second ferromagnetic layer and said fourth ferromagnetic layer have different magnetic orientations.

6. The transistor as recited in claim 1 , wherein said easy-plane ferromagnetic film comprises permalloy.

7. The transistor as recited in claim 1 , wherein said first, second, third and fourth non-magnetic layers comprise a metal or an insulator.

8. The transistor as recited in claim 1 , wherein said first, second, third and fourth ferromagnetic layers comprise a metal, an alloy or a ferromagnetic insulator.

9. The transistor as recited in claim 1 , wherein said easy-plane ferromagnetic film is rectangular or oval in said plane.

10. The transistor as recited in claim 9 , wherein said first and second metal stacks are rectangular or round in a plane beyond said plane of said ferromagnet.

11. The transistor as recited in claim 1 , wherein said transistor is utilized in one of the following: an inverter, a follower, a majority gate and a switchable OR/AND gate.

12. The transistor as recited in claim 1 , wherein said easy-plane ferromagnetic film comprises two or more ferromagnetic regions each of which individually approximates a macrospin.

13. The transistor as recited in claim 12 , wherein an output current of said transistor is controlled via an input current, wherein said input current sets a magnetic orientation of a first region of said easy-plane ferromagnetic film via spin transfer torque, wherein a magnetic orientation of said first region of said easy-plane ferromagnetic film increases a strength of a magnetic orientation of a second region of said easy-plane ferromagnetic film in response to said first region of said easy-plane ferromagnetic film being aligned with said magnetic orientation of said second region of said easy-plane ferromagnetic film thereby increasing a critical current for subsequent current flow between said output terminals or decreases a strength of said magnetic orientation of said second region of said easy-plane ferromagnetic film in response to said first region of said easy-plane ferromagnetic film being oppositely aligned with said magnetic orientation of said second region of said easy-plane ferromagnetic film thereby reducing said critical current for subsequent current flow between said output terminals, wherein in response to exceeding said critical current, said easy-plane ferromagnetic film produces an oscillatory precession about an out-of-plane axis by driving a current through said first and second metal stacks thereby increasing interlayer resistance of said first and second metal stacks and reducing current flow through said first and second metal stacks thereby producing a corresponding negative differential resistance.

14. The transistor as recited in claim 12 , wherein said third and fourth ferromagnetic layers have opposite magnetic orientations.

15. The transistor as recited in claim 12 , wherein said easy-plane ferromagnetic film comprises permalloy.

16. The transistor as recited in claim 12 , wherein said first, second, third and fourth non-magnetic layers comprise a metal or an insulator.

17. The transistor as recited in claim 12 , wherein said third and fourth ferromagnetic layers comprise a metal, an alloy or a ferromagnetic insulator.

18. The transistor as recited in claim 12 , wherein said easy-plane ferromagnetic film is rectangular or oval in said plane of said ferromagnet.

19. The transistor as recited in claim 18 , wherein said first metal stack is rectangular or oval in a plane beyond said plane of said ferromagnet.

20. The transistor in claim 18 , wherein said second metal stack is square, round or oval in a plane beyond said plane of said ferromagnet.

21. The transistor as recited in claim 12 , wherein said transistor is utilized in one of the following: an inverter, a follower, a majority gate and a switchable OR/AND gate.

22. The transistor as recited in claim 12 , wherein said transistor is utilized in non-volatile memory.

Assignees

• Univ Texas

Inventors

• Macdonald Allan
• Register Ii Leonard Franklin
• Tutuc Emanuel
• Sodemann Inti
• Chen Hua
• Mou Xuehao
• Banerjee Sanjay K

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/065 Primary

  Electricity · mapped topic

• H01L43/04

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H10N50/85

  Materials of the active region · CPC title