Semiconductor device comprising a transistor array and a termination region and method of manufacturing such a semiconductor device

Patent metadata

Field	Value
Publication number	US-9825170-B2
Application number	US-201615040624-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Feb 13, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

First claim

What is claimed is:

1. A semiconductor device formed in a semiconductor substrate having a first main surface comprising:
a transistor array comprising:
a source region;
a drain region;
a body region;
a drift zone;
a gate electrode at the body region, the gate electrode being configured to control a conductivity of a channel formed in the body region, wherein:
the gate electrode is disposed in a plurality of first trenches;
the body region and the drift zone is disposed along a first direction between the source region and the drain region;
the first direction is parallel to the first main surface;
the body region has a shape of a first ridge extending along the first direction;
a plurality of field plate trenches extending in the first direction, the field plate trenches being arranged along the first direction between the first trenches and the drain region, the field plate trenches being filled with conductive material that is electrically connected to a source contact line that is electronically coupled to a source terminal; and

a termination region comprising a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

2. The semiconductor device according to claim 1 , wherein the plurality of first trenches pattern the body region into the shape of the ridge.

3. The semiconductor device according to claim 1 , wherein an insulating layer is disposed on sidewalls and a bottom side of the termination trench and a conductive material is filled in the termination trench.

4. The semiconductor device according to claim 1 , wherein a distance between the field plate trenches is equal to or larger than a distance between the termination trench and the field plate trench adjacent to the termination trench.

5. The semiconductor device according to claim 1 , wherein a width of a portion of the termination trench is equal to a width of the field plate trenches, the width being measured in a direction perpendicular to the first direction.

6. The semiconductor device according to claim 1 , wherein a width of the termination trench is varying along the first direction.

7. The semiconductor device according to claim 1 , wherein the termination trench comprises a first termination trench portion adjacent to the first trenches and a second termination trench portion adjacent to the field plate trenches.

8. The semiconductor device according to claim 7 , wherein the width of the first termination trench portion is smaller than the width of the second termination trench portion.

9. The semiconductor device according to claim 7 , further comprising a conductive material in the first termination trench portion and a conductive material in the second termination trench portion, the conductive material in the first termination trench portion being insulated from the conductive material in the second termination trench portion and being connected with different terminals, respectively.

10. The semiconductor device according to claim 7 , wherein a depth of the first termination trench portion is smaller than a depth of the second termination trench portion.

11. The semiconductor device according to claim 7 , wherein a conductive material is disposed in the termination trench, the conductive material being insulated from adjacent semiconductor material by an insulating layer, wherein a thickness of the insulating layer is larger in the second termination trench portion than in the first termination trench portion.

12. The semiconductor device according to claim 9 , wherein the conductive material in the first termination trench portion is connected with a gate terminal, a gate connection line connecting the gate terminal with the gate electrodes being routed over the first termination trench portion.

13. The semiconductor device according to claim 1 , wherein a pitch between adjacent field plate trenches is equal to or larger than a pitch between adjacent first trenches.

14. The semiconductor device according to claim 1 , wherein the transistor array is enclosed by the termination trench.

15. The semiconductor device according to claim 1 , wherein a part of the termination trench has a greater depth than another part of the termination trench.

16. A method of manufacturing a semiconductor device comprising a transistor array and a termination region in a semiconductor substrate having a first main surface, the method comprising:
forming a source region, a drain region, a body region, and a drift zone;
forming a gate electrode at the body region, the gate electrode being configured to control a conductivity of a channel formed in the body region, the gate electrode being formed in a plurality of first trenches, the body region and the drift zone being disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the body region having the shape of a first ridge extending along the first direction;
forming a plurality of field plate trenches extending in the first direction, the field plate trenches being arranged along the first direction between the first trenches and the drain region, the field plate trenches being filled with conductive material that is electrically connected to a source contact line that is electronically coupled to a source terminal;
forming a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction; and
forming an insulating layer on sidewalls and a bottom side of the termination trench and filling a conductive material in the termination trench.

17. The method according to claim 16 , wherein the termination trench and the field plate trenches are formed using joint processing steps.

18. The method according to claim 16 , wherein the termination trench and the field plate trenches are patterned using one common photomask.

19. The method according to claim 16 , wherein forming the gate electrode comprises forming a plurality of first trenches in the first main surface, the first trenches extending in the first direction.

20. An electronic device comprising the semiconductor device according to claim 1 , the electronic device being selected from the group of a bridge circuit, a converter, an inverter and a motor drive.

Assignees

• Hirler Franz
• Meiser Andreas
• Schloesser Till
• Infineon Technologies Ag

Inventors

• Hirler Franz
• Meiser Andreas
• Schloesser Till

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H01L29/404

  Electricity · mapped topic

• H01L29/7825

  Electricity · mapped topic