Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device

Patent metadata

Field	Value
Publication number	US-9825162-B2
Application number	US-200913503861-A
Country	US
Kind code	B2
Filing date	Nov 19, 2009
Priority date	Nov 19, 2009
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers.

First claim

The invention claimed is:

1. A vertical power transistor device comprising:
a substrate formed from a III-V semiconductor material; and
a multi-layer stack at least partially accommodated in a recess of the substrate, the multi-layer stack comprising:
a semi-insulating layer grown on and in contact with the substrate, within the recess with a thickness less than a depth of the recess;
a first layer formed from a first III-V semiconductor material and grown on and in contact with the semi-insulating layer in the recess;
a second layer formed from a second III-V semiconductor material and grown on and in contact with the first layer, an interface between the first and second layers being level with or below a top edge of the substrate;
and
a heterojunction formed at the interface;
wherein the resistivity of the semi-insulating layer inhibits electrical current flow from the first layer through the semi-insulating layer to the substrate and electrical current is to flow laterally from the multi-layer stack towards regions of the substrate adjacent to sides of the recess before the electrical current flows vertically through the substrate.

2. A device as claimed in claim 1 , wherein the semi-insulating layer is formed from a III-V semiconductor material from a group consisting of: III-nitride material, binary III-nitride material, ternary III-nitride material, quaternary III-nitride material, gallium nitride comprising a p-type dopant, AlGaN, InGaN and AlInN.

3. A device as claimed in claim 1 , wherein the first layer and/or the second layer is formed from a, doped or not intentionally doped, III-V semiconductor material selected from a group consisting of: III-nitride material, binary III-nitride material, ternary III-nitride material, quaternary III-nitride material, GaN, AlGaN, InGaN; AlInN.

4. A device as claimed in claim 1 , wherein the second layer is a barrier layer.

5. A device as claimed in claim 4 , wherein the barrier layer is formed from a material selected from a group consisting of: AlGaN, InGaN and AlInN.

6. A device as claimed in claim 4 , wherein the barrier layer is formed from Al x Ga 1-x N, where x is between about 0.20 and about 0.30.

7. A device as claimed in claim 4 , wherein the multi-layer stack comprises a gallium nitride cap layer disposed adjacent the barrier layer.

8. A device as claimed in claim 1 , wherein the multi-layer stack is an epitaxial multi-layer stack.

9. A device as claimed in claim 1 , wherein the semi-insulating layer and the first layer are substantially enclosed by the substrate.

10. A device as claimed in claim 1 , wherein the substrate comprises the recess and the multi-layer stack is at least partially situated in the recess.

11. A device as claimed in claim 1 , wherein at least the semi-insulating layer is recessed in the substrate.

12. A semiconductor die comprising a first power transistor device comprising a vertical power transistor device as claimed in claim 1 and a second power transistor device comprising the vertical power transistor device as claimed in claim 1 , wherein the substrate of the first and second power transistor devices is common to both of the first and second power transistor devices, the substrate being capable of supporting a vertical drift region between a first multi-layer stack of the first power transistor device and a second multi-layer stack of the second power transistor device; and the die further comprises:
a connecting region between opposing sides of the first and second multi-layer stacks of the first and second power transistor devices for electrically coupling the heterojunctions of the first and second multi-layer stacks to the vertical drift region.

13. A die as claimed in claim 12 , wherein the connecting region comprises an ion implantation region arranged to bridge the first layer of the first multi-layer stack and the first layer of the second multi-layer stack.

14. A die as claimed in claim 13 , wherein the ion implantation region bridges the second layer and the cap layer of the first multi-layer stack and the second layer and the cap layer of the second multi-layer stack.

15. A die as claimed in claim 13 , wherein the connecting region further comprises an ohmic contact disposed adjacent the ion implantation region.

16. A method of manufacturing a vertical power transistor device, comprising:
providing a substrate formed from a nitride of a III-V semiconductor material;
etching a recess in the substrate;
growing a semi-insulating layer within the recess and in contact with the substrate with a thickness less than a depth of the recess;
growing a first layer formed from a first III-V semiconductor material within the recess of the substrate and in contact with the semi-insulating layer; and
growing a second layer formed from a second III-V semiconductor material on a top of the first layer, an interface between the first and second layers being level or below a top edge of the recess, and
wherein growing the second layer results in forming a heterojunction at the interface, and
wherein, during operation of the device, the semi-insulating layer is configured to force electrical current to flow laterally through the heterojunction towards regions of the substrate adjacent to sides of the recess before the electrical current flows vertically through the substrate.

17. A method as claimed in claim 16 , further comprising:
etching another recess in the substrate, the recess and the another recess being separated in a horizontal direction by a vertical region of the substrate.

18. A method as claimed in claim 16 , further comprising:
forming another multi-layer stack in the another recess.

19. A method as claimed in claim 18 , further comprising:
forming a connecting region so as to bridge opposing sides of the multi-layer stack and the another multi-layer stack and electrically couple the respective heterojunctions of the multi-layer stack and the another multi-layer stack to the substrate.

20. A method as claimed in claim 16 , further comprising:
forming the substrate as a free-standing substrate.

Assignees

• Renaud Philippe
• Green Bruce
• Nxp Usa Inc

Inventors

• Renaud Philippe
• Green Bruce

Classifications

• H10D84/0123

  Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs · CPC title

• H10D30/477

  Vertical HEMTs or vertical HHMTs · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

• H10D84/05

  using Group III-V technology · CPC title