Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-9825112-B2
Application number	US-201514892684-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Mar 20, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

The present disclosure discloses an array substrate, display panel and display device. The array substrate comprises: a base substrate, and peripheral routes and a plurality of pixel structures located on the base substrate. The orthographic projection of at least one pixel structure on the base substrate has an overlapping region with the periphery region in which the peripheral routes reside. The film layer where the peripheral routes reside is located between the film layer where the pixel structures reside and the base substrate or located at a side of the film layer. The array substrate allows the display region to be enlarged to cover a part or all of the periphery region where the peripheral routes reside. This can narrow down the bazel width of the display panel and even make it bezel-less.

First claim

The invention claimed is:

1. An array substrate comprising:
a base substrate, said base substrate having a display region and a periphery region;
a plurality of film layers on a top surface of said base substrate;
a plurality of pixel structures located on at least one of the film layers;
a plurality of peripheral routes located on at least one of the film layers in said periphery region;
a plurality of data lines and a plurality of gate lines on said base substrate, which intersect each other and are mutually insulative;
a thin film transistor corresponding to each said pixel structure, said thin film transistors each having a corresponding drain;
a first passivation layer;
a metal bridge; and
a second passivation layer, wherein said thin film transistors, said first passivation layer, said metal bridge, and said second passivation layer are located between said based substrate and at least one of the film layers where said pixel structures reside and are arranged in sequence on said base substrate, and wherein said pixel structures are organic electroluminescent structures;
wherein a projection of at least one said pixel structures onto the top surface of said base substrate has an overlapping region with projection of said periphery region onto the top surface of said base substrate; and
wherein at least one of the film layers where said peripheral routes reside is located between at least one of the film layers where said pixel structures reside and said base substrate wherein each said data line and each said gate line has the projection onto the top surface of said base substrate that is non-overlapping with the projection of said peripheral routes onto the top surface of said base substrate; and
wherein, for pixel structures located outside said overlapping region and the gate lines and data lines corresponding to the pixel structures, two adjacent data lines and two adjacent gate lines define one pixel structure
wherein, for at least one of the thin film transistors corresponding to one of the organic electroluminescence structure located in said overlapping region, a corresponding drain is electrically connected to said metal bridge by a first via hole penetrating said first passivation layer, and said metal bridge is electrically connected to an anode in said organic electroluminescence structure by a second via hole penetrating said second passivation layer;
wherein, for at least one of the thin film transistors corresponding to an organic electroluminescence structure located outside said overlapping region, the corresponding drain is electrically connected to an anode in said organic electroluminescence structure by a third via hole penetrating said first passivation layer and said second passivation layer.

2. The array substrate according to claim 1 , further comprising an organic resin layer arranged on said second passivation layer, said second via hole penetrating said organic resin layer and said second passivation layer, said third via hole penetrating the organic resin layer, second passivation layer and first passivation layer.

3. The array substrate according to claim 1 , wherein at least one of the film layers where said peripheral routes reside is located at a side of at least one of the film layers where said pixel structures reside, facing away from said base substrate; and wherein said array substrate further comprises: a second passivation layer, a metal bridge, a first passivation layer and a thin film transistor corresponding to each said pixel structure, arranged in sequence at least one of the film layers where said pixel structures reside facing away from said base substrate; wherein said pixel structures are organic electroluminescent structures;
wherein, for one of the thin film transistor corresponding to an organic electroluminescence structure located in said overlapping region, the corresponding drain is electrically connected to said metal bridge by a first via hole penetrating said first passivation layer, and said metal bridge is electrically connected to an anode in said organic electroluminescence structure by a second via hole penetrating said second passivation layer;
wherein, for one of the thin film transistor corresponding to an organic electroluminescence structure located outside said overlapping region, the corresponding drain is electrically connected to an anode in said organic electroluminescence structure by a third via hole penetrating said first passivation layer and said second passivation layer.

4. The array substrate according to claim 1 , further comprising: a plurality of data lines and a plurality of gate lines on said base substrate, which intersect each other and are mutually insulative; wherein each said data line and each said gate line has the projection onto the top surface of said base substrate that are non-overlapping with the projection of said peripheral routes onto the top surface of said base substrate;
and wherein a width of each said pixel structure along the direction in which said gate lines extend is larger than a distance between two adjacent data lines; and/or a width of each said pixel structure along the direction in which said data lines extend is larger than a distance between two adjacent gate lines.

5. The array substrate according to claim 4 , wherein at least one of the film layers where said peripheral routes reside is located between at least one of the film layers where said pixel structures reside and said base substrate; and wherein said array substrate further comprises: a thin film transistor corresponding to each said pixel structure and a first passivation layer, which are located between said base substrate and at least one of the film layers where said pixel structures reside and are arranged in sequence on said base substrate; wherein said pixel structures are organic electroluminescent structures; and wherein
an anode in each said organic electroluminescent structure is electrically connected to a drain in said corresponding thin film transistor by a first via hole in said first passivation layer.

6. The array substrate according to claim 4 , wherein at least one of the film layers where said peripheral routes reside is located at a side of at least one of the film layers where said pixel structures reside, facing away from said base substrate; wherein said array substrate further comprises: a first passivation layer and a thin film transistor corresponding to each said pixel structure, arranged in sequence at the side of at least one of the film layers where said pixel structures reside facing away from said base substrate; wherein each said pixel structure is an organic electroluminescent structure;
and wherein an anode in each said organic electroluminescent structure is electrically connected to a drain in said corresponding thin film transistor by a first via hole in said first passivation layer.

7. The array substrate according to claim 1 , wherein said metal bridge is bar-shaped; and wherein individual said metal bridges are located on different straight lines parallel with said gate lines.

8. The array substrate according to claim 2 , wherein said metal bridge is bar-shaped; and wherein individual said metal bridges are located on different straight lines parallel with said gate lines.

9. The array substrate according to claim 3 , wherein said metal bridge is bar-shaped; and wherein individual said metal bridges are located on different straight lines parallel with said gate lines.

10. The array substrate according to claim 5 , wherein said metal bridge is bar-shaped; and wherein individual said metal bridges are located on different straight lines parallel with said gate lines.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zou Xiangxiang

Classifications

• H01L27/3248

  Electricity · mapped topic

• H01L27/326 Primary

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic

• G08C2201/20

  Binding and programming of remote control devices · CPC title