Array substrate wherein a source electrode, drain electrode, and pixel electrode are arranged in a same layer and liquid crystal display panel having the same

Patent metadata

Field	Value
Publication number	US-9825061-B2
Application number	US-201514589002-A
Country	US
Kind code	B2
Filing date	Jan 5, 2015
Priority date	Dec 15, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

This disclosure provides an array substrate, comprising a substrate plate, and a thin film transistor and a pixel electrode formed on the substrate plate, said thin film transistor comprising a source/drain electrode, an active region and a gate electrode stacked sequentially on said substrate plate, wherein said source/drain electrode and said pixel electrode are arranged in the same layer on the substrate plate. According to this disclosure, while the properties of a high reflectivity and a high aperture ratio are guaranteed, the times of the patterning process are decreased and the process steps are saved, resulting in an improved production tempo and an effectively controlled cost. This disclosure also provides a method for fabricating an array substrate, a liquid crystal display panel comprising said array substrate and a reflective liquid crystal display.

First claim

The invention claimed is:

1. An array substrate comprising:
a substrate plate; and
a thin film transistor and a pixel electrode formed on the substrate plate, said thin film transistor comprising:
a source electrode, a drain electrode, an active region, and a gate electrode stacked sequentially on said substrate plate;

wherein said source electrode, drain electrode, and pixel electrode are arranged in a same layer on the substrate plate;
wherein the array substrate further comprises:
a data line located in a data line region and disposed in the same layer as said source and drain electrodes;
a gate line located in a gate line region and disposed in the same layer as said gate electrode; and
a passivation layer covering the gate, electrode, the gate insulating layer and the gate line; and

wherein a first via hole penetrating said gate insulating layer and said passivation layer is provided above said data line, a second via hole penetrating said passivation layer is provided above said gate line, and said first and second via holes are covered by a metal protecting layer.

2. The array substrate according to claim wherein the array substrate further comprises an active region protecting layer disposed between the substrate plate and the thin film transistor.

3. The array substrate according to claim 1 , wherein the array substrate further comprises a gate insulating layer which is disposed between the active region and the gate electrode and wherein the gate insulating layer covers the active region source electrode, drain electrode, pixel electrode, and data line.

4. The array substrate according to claim 1 , wherein an orthogonal projection of the active region onto the substrate plate is completely within an orthogonal projection of the gate electrode onto the substrate plate.

5. A liquid crystal display panel comprising:
the array substrate according to claim 1 ;
a color filter substrate; and
liquid crystals disposed between the array substrate and the color filter substrate.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Chuanxiang
• Shu Shi
• Qi Yonglian

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L27/1259

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• G02F2001/136295

  Physics · mapped topic