Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures

Patent metadata

Field	Value
Publication number	US-9824970-B1
Application number	US-201615193300-A
Country	US
Kind code	B1
Filing date	Jun 27, 2016
Priority date	Jun 27, 2016
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Disclosed are methods of forming integrated circuit (IC) structures with hybrid metallization interconnects. A dual damascene process is performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches to a gate electrode and to contact plugs on source/drain regions. A first metal is deposited into the contact holes by electroless deposition and a second metal is then deposited. Alternatively, a single damascene process is performed to form a first contact hole through a dielectric layer to a gate electrode and a first metal is deposited therein by electroless deposition. Next, a dual damascene process is performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes that extend from the trenches to contact plugs on source/drain regions. A second metal is then deposited.

First claim

What is claimed is:

1. A method comprising:
forming a field effect transistor comprising:
source/drain regions;
a channel region positioned laterally between the source/drain regions;
a gate electrode above the channel region; and
contact plugs above the source/drain regions and isolated from the gate electrode by a gate sidewall spacer;

forming a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
performing a dual damascene process to form trenches in an upper portion of the dielectric layer and contact holes extending vertically from the trenches through a lower portion of the dielectric layer, the contact holes comprising at least:
a first contact hole extending vertically to the bottom surface of the dielectric layer so as to be adjacent to the gate electrode of the field effect transistor; and,
a second contact hole extending vertically to the bottom surface of the dielectric layer so as to be immediately adjacent to a contact plug on a source/drain region of the field effect transistor;

essentially simultaneously depositing a first metal into the contact holes using an electroless deposition process, the electroless deposition process comprising activating bottom surfaces of the contact holes with an activation material and the depositing of the first metal further comprising completely filling portions of the contact holes above the activation material with the first metal; and
after the depositing of the first metal, depositing a second metal to fill the trenches, the second metal being different from the first metal.

2. The method of claim 1 , the first metal being cobalt and the second metal being copper.

3. The method of claim 1 , the activation material comprising palladium.

4. The method of claim 1 , the depositing of the first metal further comprising overfilling the contact holes with the first metal and the depositing of the second metal comprising depositing the second metal, within the trenches, above the first metal, the second metal extending laterally between and being immediately adjacent to vertical sidewalls of the trenches.

5. The method of claim 1 , further comprising, before the depositing of the second metal, depositing a barrier layer.

6. A method comprising:
forming a field effect transistor comprising:
source/drain regions;
a channel region positioned laterally between the source/drain regions;
a gate electrode above the channel region; and
contact plugs above the source/drain regions and isolated from the gate electrode by a gate sidewall spacer;

forming a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
performing a single damascene process to form at least a first contact hole extending vertically through the dielectric layer from the top surface to the bottom surface so as to be adjacent to the gate electrode of the field effect transistor;
depositing a first metal into the first contact hole using an electroless deposition process;
performing a dual damascene process to form trenches in an upper portion of the dielectric layer such that a trench traverses the first contact hole, the dual damascene process further being performed to form at least a second contact hole extending vertically from one of the trenches through a lower portion of the dielectric layer to the bottom surface so as to be immediately adjacent to a contact plug on a source/drain region of the field effect transistor; and,
depositing a second metal to fill the second contact hole and the trenches, the second metal being different from the first metal.

7. The method of claim 6 , the first metal being cobalt and the second metal being copper.

8. The method of claim 6 , the electroless deposition process further comprising activating bottom surfaces of the first contact hole with an activation material.

9. The method of claim 8 , the activation material comprising palladium.

10. The method of claim 6 , the first metal being deposited and the trenches being formed such that a top surface of the first metal in the first contact hole is approximately level with a bottom surface of the trench.

11. The method of claim 6 , the first metal being deposited and the trenches being formed such that a top surface of the first metal in the first contact hole is below a level of a bottom surface of the trench and the second metal further being deposited into the first contact hole above the second metal.

12. An integrated circuit structure comprising:
a field effect transistor comprising source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region and a gate sidewall spacer laterally surrounding the gate electrode;
contact plugs on the source/drain regions;
a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
metal wires in an upper portion of the dielectric layer;
contacts extending vertically from the metal wires through a lower portion of the dielectric layer to the bottom surface of the dielectric layer, the contacts comprising at least:
a first contact extending vertically through the lower portion of the dielectric layer to the bottom surface of the dielectric layer so as to be adjacent to the gate electrode; and,
a second contact extending vertically through the lower portion of the dielectric layer to the bottom surface of the dielectric layer so as to be immediately adjacent to a contact plug,

the first contact comprising an activation material immediately adjacent to the gate electrode and a first metal immediately adjacent to the activation material,
the metal wires and the second contact comprising a second metal that is different from the first metal,
the first contact being in a first contact opening, the second contact being in a second contact opening and the metal wires being within trenches, the second contact opening and the trenches being lined with a diffusion barrier layer, and
the first metal of the first contact extending vertically from a top of the gate electrode to a bottom of a metal wire and being physically separated from the second metal by the diffusion barrier layer.

13. The integrated circuit structure of claim 12 , the first metal being cobalt, the second metal being copper, and the activation material being palladium.

Assignees

• Globalfoundries Inc

Inventors

• Zhang Xunyuan
• Xie Ruilong

Classifications

• H10D84/83125

  the IGFETs characterised by having shared source or drain regions · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/044

  for electroless plating · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title