FinFET gate structure and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9824929-B2
Application number	US-201615382478-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Oct 28, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor fin on the semiconductor substrate; and
a n-type gate structure over the first semiconductor fin, wherein the n-type gate structure is fluorine incorporated and comprises:
a first initial layer over the first semiconductor fin;
a first high-k dielectric layer over the first initial layer and enclosed by a first gate spacer;
a n-type work function metal layer overlying the first high-k dielectric layer, the n-type work function metal layer comprising a TiAl (titanium aluminum) alloy or TaAl (tantalum aluminum) alloy, wherein an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3 when the n-type work function metal layer comprises the TiAl alloy;
a first blocking metal layer overlying the n-type work function metal layer; and
a first metal filler peripherally enclosed by the first blocking metal layer, such that the first metal filler is enclosed by a first stacked structure, wherein a side wall of the first stacked structure contains a fluorine concentration substantially from 5 atom percent (at %) to 20 at %, and a bottom of the first stacked structure contains a fluorine concentration substantially from 1 at % to 15 at %.

2. The semiconductor device of claim 1 , wherein both surfaces of the n-type work function metal layer contain an oxygen concentration substantially less than 10 atom percent (at %).

3. The semiconductor device of claim 1 , the n-type gate structure further comprising:
a capping metal layer between the first high-k dielectric layer and the n-type work function metal layer, wherein the capping metal layer comprises TiN.

4. The semiconductor device of claim 3 , the n-type gate structure further comprising:
a barrier metal layer between the capping metal layer and the n-type work function metal layer, the barrier metal layer comprising TaN (tantalum nitride); and
a TiN layer between the barrier metal layer and the n-type work function metal layer.

5. The semiconductor device of claim 1 , wherein Al atom concentrations near or at both surfaces of the n-type work function metal layer are higher than Al atom concentrations at other portions of the n-type work function metal layer.

6. The semiconductor device of claim 1 , further comprising:
a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;
a p-type gate structure over the second semiconductor fin, wherein the p-type gate structure is fluorine incorporated and comprises:
a second initial layer over the second semiconductor fin;
a second high-k dielectric layer over the second initial layer and enclosed by a second gate spacer;
a p-type work function metal layer overlying the second high-k dielectric layer, the p-type work function metal layer comprising titanium nitride (TiN), wherein an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1;
a second blocking metal layer overlying the p-type work function metal layer; and
a second metal filler peripherally enclosed by the second blocking metal layer, such that the second metal filler is enclosed by a second stacked structure, wherein a side wall of the second stacked structure contains a fluorine concentration substantially from 5 at % to 20 at %, and a bottom of the second stacked structure contains a fluorine concentration substantially from 1 at % to 15 at %.

7. The semiconductor device of claim 6 , wherein the p-type work function metal layer contains an oxygen concentration substantially less than 10 atom percent (at %).

8. The semiconductor device of claim 6 , the p-type gate structure further comprising a TiAl layer disposed between the p-type work function metal layer and the second blocking metal layer.

9. The semiconductor device of claim 6 , the p-type gate structure further comprising:
a capping metal layer between the first high-k dielectric layer and the p-type work function metal layer, wherein the capping metal layer comprises TiN.

10. The semiconductor device of claim 9 , the p-type gate structure further comprising:
a barrier metal layer between the capping metal layer and the p-type work function metal layer, wherein the barrier metal layer comprises TaN.

11. The semiconductor device of claim 6 , wherein the first metal filler or the second metal filler comprises tungsten.

12. A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor fin and a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;
a n-type gate structure comprising a first initial layer over the first semiconductor fin and enclosed by a first gate spacer, and a p-type gate structure comprising a second initial layer over the second semiconductor fin and enclosed by a second gate spacer, wherein each of the n-type gate structure and the p-type gate structure is fluorine incorporated and comprises:
a high-k dielectric layer over the first initial layer and the second initial layer;
a first TiN layer overlying the high-k dielectric layer;
a TaN layer overlying the first TiN layer;
a second TiN layer overlying the TaN layer;
a TiAl layer overlying the second TiN layer;
a third TiN layer overlying the TiAl layer; and
a metal filler peripherally enclosed by the third TiN layer, such that the metal filler is enclosed by a stacked structure, wherein a side wall of the stacked structure contains a fluorine concentration substantially from 5 at % to 20 at %, and a bottom of the stacked structure contains a fluorine concentration substantially from 1 at % to 15 at %;

wherein the TiAl layer enclosed by the first gate spacer is a n-type work function metal layer, wherein an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3; and
the second TiN layer enclosed by the second gate spacer is a p-type work function metal layer, wherein an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

13. The semiconductor device of claim 12 , wherein both surfaces of the n-type work function metal layer contain an oxygen concentration substantially less than 10 atom percent (at %).

14. The semiconductor device of claim 12 , wherein the p-type work function metal layer contains an oxygen concentration substantially less than 10 atom percent (at %).

15. The semiconductor device of claim 12 , wherein Al atom concentrations near or at both surfaces of the n-type work function metal layer are higher than Al atom concentrations at other portions of the n-type work function metal layer.

16. A method for forming a semiconductor device, the method comprising:
forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;
depositing a first initial layer enclosed by a first gate spacer over the first semiconductor fin, and a second initial layer enclosed by a second gate spacer over the second semiconductor fin;
depositing a high-k dielectric layer over the first initial layer and the second initial layer;
depositing a first TiN layer over the high-k dielectric layer;
depositing a TaN layer over the first TiN layer;
depositing a second TiN layer over the TaN layer;
depositing a TiAl layer over the second TiN layer;
depositing a third TiN layer over the TiAl layer

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jangjian Shiu-Ko
• Yu Ren-Hau
• Jeng Chi-Cherng

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/4966

  Electricity · mapped topic

• H01L21/28568

  Electricity · mapped topic