Hardware chip select training for memory using read commands

Patent metadata

Field	Value
Publication number	US-9824772-B2
Application number	US-201213727078-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Dec 26, 2012
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

First claim

What is claimed is:

1. A method of training chip select for a memory module, said method comprising:
a) programming a memory controller into a mode wherein a command signal is active for a programmable time period,
wherein said programmable time period is variable with respect to a system clock;
b) programming a programmable delay line of said chip select with a first delay value,
wherein said delay value is variable with respect to said system clock;
c) initializing said memory module;
d) sending a read command to said memory module via a command signal, and sending a chip select signal delayed by said delay value via said chip select to toggle a state of said chip select for corresponding memory accessed by said read command;
e) counting a number of data strobe signals sent by said memory module in response to said read command; and
f) determining whether said memory module is in a pass state or an error state based on a result of said counting.

2. The method of claim 1 further comprising:
resetting said memory module upon a determination of said error state;
reprogramming said programmable delay line with another delay value; and
repeating said d)-f).

3. The method of claim 1 further comprising determining a range of delay values that result in said memory module being determined to be in said pass state.

4. The method of claim 1 further comprising maintaining a frequency of said memory controller constant and maintaining a frequency of said chip select constant.

5. The method of claim 1 wherein a plurality of address signals associated with said chip select are held static for presentation to a memory module for a predetermined number of clock cycles.

6. The method of claim 1 wherein said determining comprises:
determining that said memory module is in said pass state when a count of said data strobe signals by said memory module is equal to a burst length of said read command; and
determining that said memory module is in said error state when said count is equal to zero.

7. The method of claim 1 wherein said counting is accomplished using a digital counter coupled to said memory module.

8. A non-transitory computer readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method of training chip select for a memory module, said method comprising:
a) programming a memory controller into a mode wherein a command signal is active for a programmable time period,
wherein said programmable time period is variable with respect to a system clock;
b) programming a programmable delay line of said chip select with a delay value,
wherein said delay value is variable with respect to said system clock;
c) initializing said memory module;
d) sending a read command to said memory module via a command signal, and sending a chip select signal delayed by said delay value via said chip select to toggle a state of said chip select for corresponding memory accessed by said read command;
e) counting a number of data strobe signals sent by said memory module in response to said read command; and
f) determining whether said memory module is in a pass state or an error state based on a result of said counting.

9. The computer readable storage medium of claim 8 , wherein said method further comprises:
resetting said memory module upon a determination of said error state;
reprogramming said programmable delay line another delay value; and
repeating said d)-f).

10. The computer readable storage medium of claim 8 wherein said method further comprises determining a range of delay values that result in said memory module being determined to be in said pass state.

11. The computer readable storage medium of claim 8 wherein said method further comprises maintaining a frequency of said memory controller constant and maintaining a frequency of said chip select constant.

12. The computer readable storage medium of claim 8 wherein a plurality of address signals associated with said chip select are held static for a predetermined number of clock cycles.

13. The computer readable storage medium of claim 8 wherein said determining comprises:
determining that said memory module is in said pass state when a count of said data strobe signals by said memory module is equal to a burst length of said read command; and
determining that said memory module is in said error state when said count is equal to zero.

14. The computer readable storage medium of claim 8 wherein said counting is accomplished using a digital counter coupled to said memory module.

15. A system comprising:
a processor coupled to a non-transitory computer readable storage media using a bus and executing computer readable code which causes the computer system to perform a method of training chip select for a memory module, said method comprising:
a) programming a memory controller into a mode wherein a command signal is active for a programmable time period,
wherein said programmable time period is variable with respect to a system clock;
b) programming a programmable delay line of said chip select with a delay value,
wherein said delay value is variable with respect to said system clock;
c) initializing said memory module;
d) sending a read command to said memory module via a command signal, and sending a chip select signal delayed by said delay value via said chip select to toggle a state of said chip select for corresponding memory accessed by said read command;
e) counting a number of data strobe signals sent by said memory module in response to said read command; and
f) determining whether said memory module is in a pass state or an error state based on a result of said counting.

16. The system of claim 15 , wherein said method further comprises:
resetting said memory module upon a determination of said error state;
reprogramming said programmable delay line with another delay value; and
repeating said d)-f).

17. The system of claim 15 wherein said method further comprises determining a range of delay values that result in said memory module being determined to be in said pass state.

18. The system of claim 15 wherein said method further comprises maintaining a frequency of said memory controller constant and maintaining a frequency of said chip select constant.

19. The system of claim 15 wherein:
said memory module is in said pass state when a count of said data strobe signals by said memory module is equal to a burst length of said read command; and
said memory module is in said error state when said count is equal to zero.

20. The system of claim 15 wherein:
said counting is accomplished using a digital counter coupled to said memory module; and
a plurality of address signals associated with said chip select are held static for a predetermined number of clock cycles.

Assignees

• Nvidia Corp

Inventors

• Malladi Venkata Ramana
• Cheng Tony Yuhsiang
• Raghava Sharath
• Kumar Ambuj
• Sahni Arunjit
• Lam Paul

Classifications

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C11/40

  using transistors · CPC title

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title