Apparatuses and methods for flexible fuse transmission

Patent metadata

Field	Value
Publication number	US-9824770-B1
Application number	US-201715493772-A
Country	US
Kind code	B1
Filing date	Apr 21, 2017
Priority date	Sep 14, 2016
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

First claim

What is claimed is:

1. An apparatus comprising:
a fuse data bus;
an fuse circuit coupled to the fuse data bus, the fuse circuit comprising a plurality of fuse groups, each fuse group of the plurality of fuse groups comprising a first fuse array and at least one second fuse array, the first fuse array of each fuse group of the plurality of fuse groups being configured to store bank selection information, the at least one second fuse array of each fuse group of the plurality of fuse groups being configured to store defective address information, and the fuse circuit being configured to access each fuse group of the plurality of fuse groups to transfer the bank selection information and the defective address information successively onto the fuse data bus from the first fuse array and the at least one second fuse array of an accessed fuse group, respectively;
a plurality of control lines;
a decoding circuit coupled to the fuse data bus, the decoding circuit being configured to provide a signal at an enable level to a control line of the plurality of control lines responsive to the bank selection information on the fuse data bus at least until transfer of the defective address information from the at least one second fuse array onto the fuse data is completed; and
a plurality of redundant latch circuits provided correspondingly to a plurality of memory banks, each redundant latch circuit of the plurality of redundant latch circuits comprises a pointer circuit and a plurality of latches, the pointer circuit being coupled to an associated control line of the plurality of control lines, each latch of the plurality of latches being coupled to the fuse data bus, the pointer circuit of each redundant latch circuit of the plurality of redundant latch circuits being configured to designate one latch of the plurality of latches of an associated redundant latch circuit of the plurality of redundant latch circuits as an active latch and to update the active latch among the plurality of latches responsive to a fuse load signal to cause respective active latch to latch respective defective address information on the fuse data bus, during the associated control line of the plurality of control lines being provided with the signal at the enable level.

2. The apparatus of claim 1 , wherein the decoding circuit comprises a plurality of decoders, each decoder of the plurality of decoders being coupled between the fuse data bus and an associated control line of the plurality of control lines.

3. The apparatus of claim 2 , wherein each decoder of the plurality of decoders comprises:
a gate circuit configured to decode the bank selection information; and
a latch circuit coupled between the gate circuit of an associated decoder of the plurality of decoders and an associated control line of the plurality of control lines, the latch circuit configured to latch an output signal of the gate circuit responsive to a latch enable signal.

4. The apparatus of claim 1 , wherein each fuse array of the first fuse array and the at least one second fuse array includes a flag bit, the flag bit of the first fuse array being configured to store a first logic level to indicate that the first fuse array stores the bank selection information, and the flag bit of the at least one second fuse array being configured to store a second logic level to indicate that the second fuse array stores the defective address information.

5. The apparatus of claim 4 , wherein the decoding circuit comprises a plurality of decoders, each decoder of the plurality of decoders comprising:
a gate circuit configured to decode the bank selection information; and
a latch circuit coupled between the gate circuit of an associated decoder of the plurality of decoders and an associated control line of the plurality of control lines, the latch circuit configured to latch an output signal of the gate circuit responsive to the flag bit storing the first logic level.

6. The apparatus of claim 1 , wherein the pointer circuit of each redundant latch circuit of the plurality of redundant latch circuits comprises a plurality of flip-flops (FFs) provided correspondingly to the plurality of latches of an associated redundant latch circuit of the plurality of redundant latch circuits, each latch of the plurality of latches being activated as the activated latch to latch the defect address information on the bus responsive to an associated FF of the plurality of FFs providing a signal at an active level.

7. The apparatus of claim 6 , wherein an FF providing the signal at the active level is changed among the plurality of FFs of each redundant latch circuit of the plurality of redundant latch circuits when the defective address information belonging to an associated latch circuit of the plurality of latch circuits is transferred onto the fuse data bus.

8. The apparatus of claim 1 , wherein the fuse circuit further comprises at least one additional fuse array provided correspondingly to at least one of the plurality of redundant latch circuits, the at least one additional fuse array comprising a plurality of bits corresponding respectively to the plurality of latches of the at least one of the plurality of redundant latch circuits, each bit of the plurality of bits of the additional fuse array storing one of first information and second information, the first information being indicative of a corresponding latch of the plurality of latches being valid, and the second information being indicative of the corresponding latch of the plurality of latches being invalid.

9. The apparatus of claim 8 , wherein the fuse circuit is further configured to access the additional fuse array before accessing each fuse group of the plurality of fuse groups to cause the at least one of the plurality of redundant latch circuits to store contents of the plurality of bits of the additional fuse latch.

10. The apparatus of claim 9 , wherein the pointer circuit of the at least one of the plurality of redundant latch circuits is further configured to disable designating one or more latches of the plurality of latches of the at least one of the plurality of redundant latch circuits indicated as being invalid by the second information as an active latch.

11. An apparatus comprising:
a fuse data bus;
a plurality of control lines;
an fuse circuit coupled to the fuse data bus, the fuse circuit comprising a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store bank control information and defective address information in pair, the fuse circuit being configured to access each fuse array of the plurality of fuse arrays to transfer the bank control information and the defective address information in pair onto the fuse data bus from an accessed fuse array of the plurality of fuse arrays, the fuse circuit being further configured to provide a signal at an enable level to a control line of the plurality of control lines responsive to the bank control information transferred onto the fuse data bus at least until the bank control information transferred onto the fuse data bus requests updating; and
a plurality of redundant latch circuits provided correspondingly to a plurality of memory banks, each redundant latch circuit of the plurality of redundant latch circuits comprising a pointer circuit and a plurality of latches, the pointer circuit being coupled to an associated control line of the plurality of control lines, each latch of the plurality of latches being coupled to the fuse data bus, the pointer circuit being configured to designate a latch of the plurality of latches of an associated redundant latch circuit of the plurality of redundant latch circuits as an active latch an

Assignees

• Micron Technology Inc

Inventors

• Fujiwara Yoshinori
• Yoshida Kenji
• Someya Minoru
• Noda Hiromasa

Classifications

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C29/78

  using programmable devices · CPC title