Gate driver unit, gate driver circuit and driving method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9824656-B2
Application number	US-201615233487-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Feb 1, 2016
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A gate driver unit, a gate driver circuit and a driving method thereof, and a display device are disclosed. In the gate driver unit, an input module is configured to pull up a voltage at a pulling-up node to a high level, the pulling-up node being a connection node of an output end of the input module and a control end of an output module; the output module is configured to output a gate driving signal under a control of a second dock signal; a pulling-up module is configured to reverse the voltage at the pulling-up node under a control of a fourth clock signal; a pulling-down module is configured to reverse a voltage at an output end of the output module under a control of the second clock signal; and a reset module is configured to reset the output end of the output module.

First claim

What is claimed is:

1. A gate driver unit, comprising an input module, an output module, a pulling-up module, a pulling-down module and a reset module, wherein,
the input module is connected with a first signal input end, a second signal input end, a first clock signal input end, a third clock signal input end and a pulling-up node, respectively, and is configured to pull up a voltage at the pulling-up node to a high level, the pulling-up node being a connection node of an output end of the input module and a control end of the output module;
the output module is connected with a second clock signal input end, the pulling-up node and an output end of the gate driver unit, respectively, and is configured to output a gate driving signal under a control of a second clock signal input from the second clock signal input end, the output end of the gate driver unit being a connection node of an output end of the pulling-down module and an output end of the output module;
the pulling-up module is connected with a fourth clock signal input end and the pulling-up node, respectively, and is configured to reverse the voltage at the pulling-up node under a control of a fourth clock signal input from the fourth clock signal input end;
the pulling-down module is connected with the second clock signal input end, the pulling-up node, the output end of the gate driver unit and a reference voltage input end, and is configured to reverse a voltage at the output end of the output module under a control of the second clock signal input from the second dock signal input end; and
the reset module is connected with the first clock signal input end, the third clock signal input end and the reference voltage input end, and is configured to reset the output end of the output module.

2. The gate driver unit of claim 1 , wherein the input module comprises a first transistor and a second transistor, wherein,
the first transistor has a gate connected with the first clock signal input end, a first electrode connected with the first signal input end, and a second electrode connected with the pulling-up node; and
the second transistor has a gate connected with the third clock signal input end, a first electrode connected with the second signal input end, and a second electrode connected with the pulling-up node.

3. The gate driver unit of claim 1 , wherein the output module comprises a third transistor and a first capacitor, wherein,
the third transistor has a gate connected with the pulling-up node, a first electrode connected with the second clock signal input end, and a second electrode connected with the pulling-down module and the reset module, a connection node of the second electrode of the third transistor with the pulling-down module and the reset module being the output end of the output module; and
the first capacitor has a first end connected with the pulling-up node and a second end connected with the output end of the output module.

4. The gate driver unit of claim 1 , wherein the pulling-up module comprises a fourth transistor, a gate of which is connected with a first electrode thereof and further connected with the fourth clock signal input end, and a second electrode of the fourth transistor is connected with the pulling-up node.

5. The gate driver unit of claim 1 , wherein the pulling-down module comprises a second capacitor, a fifth transistor, a sixth transistor and a seventh transistor, wherein,
the second capacitor has a first end connected with the second clock signal input end and a second end connected with a second electrode of the fifth transistor, a pulling-down node being a connection node of the second end of the second capacitor with the second electrode of the fifth transistor;
the fifth transistor has a gate connected with the pulling-up node, a first electrode connected with the reference voltage input end, and a second electrode connected with the second end of the second capacitor;
the sixth transistor has a gate connected with the pulling-down node, a first electrode connected with the reference voltage input end, and a second electrode connected with the pulling-up node; and
the seventh transistor has a gate connected with the pulling-down node, a first electrode connected with the reference voltage input end, and a second electrode connected with the output end of the gate driver unit.

6. The gate driver unit of claim 1 , wherein the reset module comprises an eighth transistor and a ninth transistor, wherein,
the eighth transistor has a gate connected with the first clock signal input end, a first electrode connected with the reference voltage input end, and a second electrode connected with the output end of the gate driver unit; and
the ninth transistor has a gate connected with the third clock signal input end, a first electrode connected with the reference voltage input end, and a second electrode connected with the output end of the gate driver unit.

7. A gate driver circuit, comprising a plurality of gate driver units of claim 1 which are cascaded, and each gate driver unit corresponds to a gate line and provides a gate driving signal to the corresponding gate line.

8. A display device, comprising the gate driver circuit of claim 7 .

9. A driving method of a gate driver circuit comprising a plurality of the gate driver units of claim 1 , wherein, when an N-th gate line is being driven, the driving method of the gate driver unit corresponding to the N-th gate line comprises an input and hold stage, an output stage and a reset stage, wherein,
in the input and hold stage, the input module, under a control of the first clock signal, receives an output signal from the output module of the gate driver unit corresponding to an (N−1)-th gate line as an input signal, and stores the input signal at the pulling-up node; and the pulling-up module holds a voltage at the pulling-up node under a control of the fourth clock signal;
in the output stage, the output module outputs a gate driving signal for the stage of its own to drive the N-th gate line under a control of the second clock signal; and
in the reset stage, under a control of the third clock signal, an output signal of the output module of the gate driver unit corresponding to an (N+1)-th gate line is used as a reset signal to reset a voltage at the output end of the output module of the gate driver unit corresponding to the N-th gate line.

10. The driving method of the gate driver circuit of claim 9 , wherein, when a gate line other than the N-th gate line is being driven, the driving method of the gate driver unit corresponding to the N-th gate line further comprises a level hold stage and a level reverse stage, wherein,
in the level hold stage, voltages at the pulling-up node and the pulling-down node are hold at a low level under a control of the first clock signal and the third clock signal; and
in the level reverse stage, the voltages at the pulling-up node and the pulling-down node are reversed under a control of the fourth clock signal.

11. The driving method of the gate driver circuit of claim 9 , wherein duration of active level of each of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal is a quarter period, and the active level is a high level.

12. The driving method of the gate driver circuit of claim 9 , wherein a forward driving mode or a backward driving mode is employed, wherein,
in the forward driving mode, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are successively set to be the active level, and the active levels of these clock signals are successively lagged a quarter period; an

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Chen Mo
• Liu Jinliang
• Zhao Jian

Classifications

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title