Liquid crystal display and method for driving the same

Patent metadata

Field	Value
Publication number	US-9824653-B2
Application number	US-201414533855-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Jan 8, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A liquid crystal display includes: a display panel including data lines, scan lines and a plurality of pixels connected to the data lines and the scan lines; a scan driver configured to supply scan signals to the scan lines; a data driver configured to supply data voltages to the data lines; and a timing controller configured to control operation timings of the scan driver and the data driver, where the timing controller is configured to output a plurality of scan output enable signals to the scan driver, and the scan driver is configured to supply odd scan signals to odd scan lines based on a first scan output enable signal of the scan output enable signals and to supply even scan signals to even scan lines based on a second scan output enable signal of the scan output enable signals.

First claim

What is claimed is:

1. A liquid crystal display, comprising:
a display panel comprising data lines, scan lines, and a plurality of pixels connected to the data lines and the scan lines;
a scan driver configured to supply scan signals to the scan lines;
a data driver configured to supply data voltages to the data lines; and
a timing controller configured to control operation timings of the scan driver and the data driver,
wherein the timing controller is configured to output a plurality of scan output enable signals to the scan driver,
wherein the scan driver is configured to supply odd scan signals to odd scan lines based on a first scan output enable signal of the scan output enable signals, to supply even scan signals to even scan lines based on a second scan output enable signal of the scan output enable signals, and to supply the scan signals to the scan lines in a non-sequential order in a transition minimization addressing mode.

2. The liquid crystal display of claim 1 , wherein
a phase of the first scan output enable signal is different from a phase of the second scan output enable signal, or
the second scan output enable signal is a signal delayed from the first scan output enable signal.

3. The liquid crystal display of claim 1 , wherein
the scan driver is configured to sequentially supply the scan signals to the scan lines in a sequential addressing mode.

4. The liquid crystal display of claim 3 , wherein the timing controller is configured to output a scan start signal and a scan clock signal to the scan driver.

5. The liquid crystal display of claim 4 , wherein phases of the first and second scan output enable signals in the sequential addressing mode is different from phases of the first and second scan output enable signals in the transition minimization addressing mode.

6. The liquid crystal display of claim 5 , wherein the scan driver comprises:
a D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal;
odd AND gates coupled to the odd scan lines, wherein the odd AND gates are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the D flip-flop circuit, and; and
even AND gates coupled to the even scan lines, wherein the even AND gates are configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the D flip-flop circuit.

7. The liquid crystal display of claim 5 , wherein the scan driver comprises:
a first scan drive circuit configured to receive the scan start signal, the scan clock signal and the first scan output enable signal; and
a second scan drive circuit configured to receive the scan start signal, the scan clock signal and the second scan output enable signal.

8. The liquid crystal display of claim 7 , wherein the first scan drive circuit comprises:
a first D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal; and
a first AND gate group coupled to the odd scan lines, wherein the first AND gate group is configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the first D flip-flop circuit.

9. The liquid crystal display of claim 8 , wherein the second scan drive circuit comprises:
a second D flip-flop circuit configured to sequentially output pulse signals according to the scan clock signal in response to the scan start signal; and
a second AND gate group coupled to the even scan lines, wherein the second AND gate group is configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the second D flip-flop circuit.

10. The liquid crystal display of claim 4 , wherein the scan driver is configured
to supply scan signals to (4u-3)-th scan lines based on the first scan output enable signal,
to supply scan signals to (4u-2)-th scan lines based on the second scan output enable signal,
to supply scan signals to (4u-1)-th scan lines based on a third scan output enable signal of the scan output enable signals, and
to supply scan signals to (4u)-th scan lines based on a fourth scan output signal of the scan output enable signals,
wherein u is a natural number.

11. The liquid crystal display of claim 10 , wherein
phases of the first to fourth scan output enable signals are different from each other, or
the first to fourth scan output enable signals are signals sequentially delayed from one another.

12. The liquid crystal display of claim 10 , wherein phases of the first to fourth scan output enable signals in the sequential addressing mode are different from phases of the first to fourth scan output enable signals in the transition minimization addressing mode.

13. The liquid crystal display of claim 12 , wherein the scan driver comprises:
a D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal;
(4u-3)-th AND gates coupled to the (4u-3)-th scan lines, wherein the (4u-3)-th AND gates are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the D flip-flop circuit;
(4u-2)-th AND gates coupled to the (4u-2)-th scan lines, wherein the (4u-2)-th AND gates are configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the D flip-flop circuit;
(4u-1)-th AND gates coupled to the (4u-1)-th scan lines, wherein the (4u-1)-th AND gates are configured to output a result of AND operation for an inversion signal of the third scan output enable signal and the pulse signals from the D flip-flop circuit; and
(4u)-th AND gates coupled to the (4u-2)-th scan lines, wherein the (4u-2)-th AND gates are configured to output a result of AND operation for an inversion signal of the fourth scan output enable signal and the pulse signals from the D flip-flop circuit.

14. The liquid crystal display of claim 12 , wherein the scan driver comprises:
a first scan drive circuit configured to receive the scan start signal, the scan clock signal, and the first and third scan output enable signals; and
a second scan drive circuit configured to receive the scan start signal, the scan clock signal, and the second and fourth scan output enable signal.

15. The liquid crystal display of claim 14 , wherein the first scan drive circuit comprises:
a first D flip-flop circuit configured to sequentially output pulse signals according to the scan clock signal in response to the scan start signal; and
a first AND gate group comprising:
odd AND gates coupled to the (4u-3)-th scan lines, wherein the odd AND gates of the first AND gate group are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the first D flip-flop circuit; and
even AND gates coupled to the (4u-1)-th scan lines, wherein the even AND gates of the first AND gate group are configured to output a result of AND operation for an inversion signal of the third scan output enable signal and the pulse signals from the first D flip-flop circuit.

16. The liquid crystal display of claim 15 , wherein the second scan drive circuit comprises:
a second D flip-flop circuit configured to sequentially output pulse signals according to t

Assignees

• Samsung Display Co Ltd

Inventors

• Park Su-Hyeong
• Seo Ji-Myoung
• Jung Ho-Yong
• Lee Eun-Ho
• Park Cheol-Woo

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3614 Primary

  Control of polarity reversal in general · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• A47G9/1036

  with cooling or heating means · CPC title

• A47G9/1045

  shaped as, combined with, or convertible into other articles, e.g. dolls, sound equipments, bags or the like · CPC title