Dynamic subroutine linkage optimizing shader performance

Patent metadata

Field	Value
Publication number	US-9824484-B2
Application number	US-201615208328-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Jun 27, 2008
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.

First claim

What is claimed is:

1. A method of allocating memory registers to shader instances, comprising:
generating program code for a simple shader definition;
generating program code for a complex shader definition;
storing the program code for the simple shader definition and the program code for the complex shader definition at respective locations in a table;
wherein upon execution, the program code:
utilizes a pointer to select either the program code for the simple shader definition or the program code for the complex shader definition within the table, and
allocates memory for the selected program code, wherein a number of registers associated with the memory and allocated for the selected program code depends on the selected program code, wherein a greater number of registers is allocated when the program code for the complex shader definition is selected, and a lesser number of registers is allocated when the program code for the simple shader definition is selected;
wherein generating program code for the simple shader definition and the complex shader definition comprises generating inline code.

2. The method of claim 1 , further comprising providing a graphics processing unit (GPU) driver with one or more tables defining usage points and indicating definitions of the simple shader definition and the complex shader definition.

3. The method of claim 1 , wherein the program code for the simple shader definition is an instance of the simple shader definition.

4. The method of claim 3 , wherein the program code for the complex shader definition is an instance of the complex shader definition.

5. The method of claim 4 , further comprising binding the simple shader instance and the complex shader instance to a pipeline.

6. The method of claim 5 , wherein binding comprises storing in the table by a function type and a call location each use of both the simple shader instance and the complex shader instance.

7. One or more computer-storage memory having computer-executable instructions embodied thereon for executing a method of allocating memory registers to shader instances, comprising:
generating program code for a simple shader definition;
generating program code for a complex shader definition;
storing the program code for the simple shader definition and the program code for the complex shader definition at respective locations in a table;
wherein upon execution, the program code:
utilizes a pointer to select either the program code for the simple shader definition or the program code for the complex shader definition within the table, and
allocates memory for the selected program code, wherein a number of registers associated with the memory and allocated for the selected program code depends on the selected program code, wherein a greater number of registers is allocated when the program code for the complex shader definition is selected, and a lesser number of registers is allocated when the program code for the simple shader definition is selected;
wherein generating program code for the simple shader definition and the complex shader definition comprises generating inline code.

8. The one or more computer-storage memory of claim 7 , further comprising providing a graphics processing unit (GPU) driver with one or more tables defining usage points and indicating definitions of the simple shader definition and the complex shader definition.

9. The one or more computer-storage memory of claim 7 , wherein the program code for the simple shader definition is an instance of the simple shader definition.

10. The one or more computer-storage memory of claim 9 , wherein the program code for the complex shader definition is an instance of the complex shader definition.

11. The one or more computer-storage memory of claim 10 , further comprising binding the simple shader instance and the complex shader instance to a pipeline.

12. The one or more computer-storage memory of claim 11 , wherein binding comprises storing in the table by a function type and a call location each use of both the simple shader instance and the complex shader instance.

13. A computing device configured to allocate memory registers to shader instances, comprising:
a memory unit with one or more memory registers;
one or more processors configured to:
generate program code for a simple shader definition;
generate program code for a complex shader definition;
store the program code for the simple shader definition and the program code for the complex shader definition at respective locations in a table;
wherein upon execution, the program code:
utilizes a pointer to select either the program code for the simple shader definition or the program code for the complex shader definition within the table, and
allocates memory for the selected program code, wherein a number of registers associated with the memory and allocated for the selected program code depends on the selected program code, wherein a greater number of registers is allocated when the program code for the complex shader definition is selected, and a lesser number of registers is allocated when the program code for the simple shader definition is selected;
wherein generate program code for the simple shader definition and the complex shader definition comprises generate inline code.

14. The computing device of claim 13 , further comprising providing a graphics processing unit (GPU) driver with one or more tables defining usage points and indicating definitions of the simple shader definition and the complex shader definition.

15. The computing device of claim 13 , wherein the program code for the simple shader definition is an instance of the simple shader definition.

16. The computing device of claim 15 , wherein the program code for the complex shader definition is an instance of the complex shader definition.

17. The computing device of claim 16 , further comprising binding the simple shader instance and the complex shader instance to a pipeline.

18. The computing device of claim 17 , wherein binding comprises storing in the table by a function type and a call location each use of both the simple shader instance and the complex shader instance.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Oneppo Michael V
• Peeper Craig
• Bliss Andrew L
• Rapp John L
• Lacey Mark M

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06F9/449

  Object-oriented method invocation or resolution · CPC title

• G06T15/80

  Shading · CPC title