Event specific page faults for interrupt handling

Patent metadata

Field	Value
Publication number	US-9824019-B2
Application number	US-201514750328-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.

First claim

The invention claimed is:

1. At least one non-transitory machine-readable storage medium comprising instructions that when executed by a computing-system, cause the computing-system to:
add a pseudo-entry stub (PES) address to an execution stack corresponding to a processor element, the PES address to identify a non-executable address;
add an interrupt service routine (ISR) address to the execution stack in a position ahead of the PES address, the ISR address to identify a location of an ISR;
restore one or more states of the processor element based on one or more first states of the processor element to be indicated by an ISR information element; and
send a control signal to the processor element to cause the processor element to execute the ISR.

2. The at least one non-transitory machine-readable storage medium of claim 1 , comprising instructions that when executed by the computing system, cause the computing system to receive a first interrupt, the first interrupt to correspond to an interrupted process, the ISR to correspond to the first interrupt.

3. The at least one non-transitory machine-readable storage medium of claim 2 , comprising instructions that when executed by the computing system, cause the computing system to generate the ISR information element in response to receipt of the first interrupt, the ISR information element to include an indication of the one or more first states of the processor element and an instruction pointer to include an indication of the interrupted process.

4. The at least one non-transitory machine-readable storage medium of claim 3 , comprising instructions that cause the computing-system to determine whether the first interrupt corresponds to a PES address page fault and select the pseudo-entry stub (PES) address, the selecting the pseudo-entry stub (PES) address and the adding the PES address to the execution stack based on a determination that the first interrupt does not correspond to a PES address page fault.

5. The at least one non-transitory machine-readable storage medium of claim 4 , comprising instructions that cause the computing-system to:
identify an index in a bitwise array of lock bits;
lock the index; and
select the index as the PES address.

6. The at least one non-transitory machine-readable storage medium of claim 5 , the bitwise array of lock bits comprising a memory page of addresses not executable by the processing element.

7. The at least one non-transitory machine-readable storage medium of claim 5 , comprising instructions that cause the computing-system to:
identify a first free position in the bitwise array of lock bits; and
select the first free position as the index.

8. The at least one non-transitory machine-readable storage medium of claim 7 , comprising instructions that cause the computing-system to store an indication of the location of the ISR information element in the first free position.

9. The at least one non-transitory machine-readable storage medium of claim 5 , comprising instructions that cause the computing-system to:
execute one or more ISR instrumentation operations;
retrieve, based on a received second interrupt, the instruction pointer from the ISR information element;
add the instruction pointer to the execution stack;
restore one or more states of the processor element based on the one or more first states; and
send a control signal to the processor element to cause the processor element to execute the instruction pointer.

10. The at least one non-transitory machine-readable storage medium of claim 9 , comprising instructions that cause the computing-system to determine whether the first interrupt corresponds to a PES address page fault, the retrieving the instruction pointer from the ISR information element, the adding the instruction pointer to the execution stack, the restoring one or more states of the processor element based on the one or more first states, and the sending the control signal to the processor element to cause the processor element to execute the instruction pointer based on a determination that the first interrupt does correspond to a PES address page fault.

11. The at least one non-transitory machine-readable storage medium of claim 10 , comprising instructions that cause the computing-system to:
derive a difference between the PES address and a base address of the PES array;
determine the index as the quotient of the difference divided by the size of the PES array; and
retrieve the instruction pointer based on the index.

12. The at least one non-transitory machine-readable storage medium of claim 3 , comprising instructions that cause the computing-system to:
retrieve a first interrupt descriptor table (IDT) address from an interrupt descriptor table register (IDTR), the IDT address to identify a location of an original IDT;
add an indication of the IDT address to the ISR information element; and
load a second IDT address to the IDTR, the second IDT address to identify a location of a modified IDT, the modified IDT to include a plurality of interrupt vectors.

13. An apparatus, comprising:
logic, a portion of which is implemented in hardware, the logic to comprise:
an ISR loading component to:
add an indication of an instruction pointer to an interrupt service routine (ISR) information element, the instruction pointer to correspond to a process interrupted by a first interrupt; and
add an ISR address to an execution stack corresponding to a processor element in a position ahead of a pseudo-entry stub (PES) address, the ISR address to identify a location of an ISR, the PES address to identify a non-executable address; and an ISR execution component to:
restore one or more states of the processor element based on one or more first states of the processor element to be identified by the ISR information element; and
send a control signal to the processor element to cause the processor element to execute the ISR.

14. The apparatus of claim 13 , comprising:
a common exit handler component to generate, based on the first interrupt, the ISR information element, the ISR information element to include an indication of the one or more first states of the processor element; and
a PES component to:
select the PES address; and
add the PES address to the execution stack.

15. The apparatus of claim 14 , the common exit handler component to determine whether the first interrupt corresponds to a PES address page fault; and the PES component to select the pseudo-entry stub (PES) address and add the PES address to the execution stack based on a determination that the first interrupt does not correspond to a PES address page fault.

16. The apparatus of claim 15 , the PES component to identify a first free position in a bitwise array of lock bits; lock the first free position; and select the first free position as the PES address; and the common exit handler component to store an indication of the location of the ISR information element in the first free position, the bitwise array of lock bits comprising a memory page of addresses not executable by the processing element.

17. The apparatus of claim 15 , comprising:
an instrumentation component to execute one or more ISR instrumentation operations; and
an instrumentation exit component to:
retrieve, based on a received second interrupt, the instruction pointer from the ISR information element;
add the instruction pointer to the execution stack;
restore one or more states of the processor element based on the one or more first states; and
send a control signal to the processor element t

Assignees

• Intel Corp

Inventors

• Castelino Manohar R
• Hinman John

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title