Cache control apparatus and method

Patent metadata

Field	Value
Publication number	US-9824017-B2
Application number	US-201414253349-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Nov 20, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

First claim

What is claimed is:

1. A cache control apparatus for one of a plurality of caches, respectively used by one of a plurality of processors for accessing a memory, for maintaining data coherency of the plurality of caches, each cache including an instruction cache and a tag memory, the apparatus comprising:
a coherency controller including an MESI (modified exclusive shared invalid) register that is included in the instruction cache of the one cache, and is configured to store one of a modified state, an exclusive state, a shared state, and an invalid state for each cache line of the instruction cache;
a coherency interface connected to the coherency controller, and configured to transmit and receive broadcast address information including a broadcasted address for a cache read or write operation, an index address that corresponds to the broadcast address and that indicates a location in the tag memory for internally storing the cache read or write operation, read or write information, and hit or miss information of another one of the plurality of caches to and from the instruction cache, wherein
the coherency controller is configured to,
upon detecting that a cache line of the instruction cache is in the modified state and is required to be emptied by using a least recently used (LRU) controller, write information in the cache line to the memory,
modify the modified state of the cache line to the invalid state, and
transmit a signal for requesting access to a coherency bus and a signal for allowing an occupation of the coherency bus.

2. The cache control apparatus of claim 1 , further comprising a miss controller configured to receive one of a read start instruction signal or a write start instruction signal from the coherency controller.

3. The cache control apparatus of claim 2 , wherein the coherency controller
analyzes a plurality of pieces of information including the broadcast address information, the index address, the read or write information, and the hit or miss information of the another cache, each piece of information being received from the coherency interface, and
transmits the read start instruction signal or the write start instruction signal to the miss controller, based on a result of the analysis.

4. The cache control apparatus of claim 3 , wherein,
when the instruction cache is in the invalid state and a read miss signal is received from a tag memory controller, the coherency controller transmits the broadcast address information, the index address, the read or write information, and the hit or miss information of the instruction cache to the another cache through the coherency interface,
when state information of the another cache which is received through the coherency interface indicates the shared state, the coherency controller modifies the invalid state of the instruction cache into the shared state, transmits the read start instruction signal to the miss controller, and reads a cache line from the memory, and
when the state information of the another cache which is received through the coherency interface indicates the exclusive state, the coherency controller modifies the invalid state of the instruction cache into the exclusive state, transmits the read start instruction signal to the miss controller, and reads the cache line from the memory.

5. The cache control apparatus of claim 3 , wherein when the instruction cache is in the invalid state and a write miss signal is received from a tag memory controller, the coherency controller transmits an invalidation signal through the coherency interface, receives a backward response signal for the transmitted invalidation signal, transmits the read start instruction signal to the miss controller, and modifies the invalid state into the modified state.

6. The cache control apparatus of claim 3 , wherein when the instruction cache is in the shared state and a write hit signal is received from a tag memory controller, the coherency controller transmits an invalidation signal through the coherency interface, receives a backward response signal for the transmitted invalidation signal, transmits the read start instruction signal to the miss controller to read a cache line from the memory, and modifies the shared state into the modified state.

7. The cache control apparatus of claim 6 , wherein when a read hit signal or a snoop read hit signal is received, the coherency controller maintains the shared state.

8. The cache control apparatus of claim 3 , wherein,
when the instruction cache is in the modified state and a snoop read hit signal is received, the coherency controller transmits the write start instruction signal to the miss controller to write information of a cache line in the memory, and modifies the modified state into the shared state, and
when the instruction cache is in the modified state and a snoop invalidation hit signal is received, the coherency controller transmits the write start instruction signal to the miss controller to write the information of the cache line in the memory, and modifies the modified state into the invalid state.

9. The cache control apparatus of claim 8 , wherein when a read hit signal or a write hit signal is received from a tag memory controller, the coherency controller maintains the modified state.

10. The cache control apparatus of claim 3 , wherein, in a case where the instruction cache is in the exclusive state,
when read hit information is received from a tag memory controller, the coherency controller maintains the exclusive state,
when write hit information is received from the tag memory controller, the coherency controller modifies the exclusive state of the instruction cache into the modified state,
when snoop invalidation hit information is received through the coherency interface, the coherency controller modifies the exclusive state into the invalid state, and
when snoop read hit information is received through the coherency interface, the coherency controller modifies the exclusive state into the shared state.

11. A cache control method of a cache control apparatus including a cache controller for one of a plurality of caches, respectively used by one of a plurality of processors for accessing a memory, for maintaining data coherency of the plurality of caches, each cache including an instruction cache and a tag memory, the method comprising:
performing a hit/miss receiving operation of receiving a hit signal or a miss signal of the instruction cache of the one cache from a tag memory controller;
performing a transmission operation of transmitting broadcast address information including a broadcasted address for a cache read or write operation, an index address that corresponds to the broadcast address and that indicates a location in the tag memory for internally storing the cache read or write operation, read or write information, and hit or miss information to another one of the plurality of caches through a coherency interface by requesting a coherency bus as a dedicated communication channel for maintaining the data coherency of the plurality of caches, based on the received hit signal or miss signal;
performing a reception operation of receiving the broadcast address information, the index address, the read or write information, and the hit or miss information of the another cache through the coherency interface; and
performing a state modification and start instruction signal transmitting operation of analyzing the received broadcast address information, index address, read or write information, and hit or miss information to modify state information of the instruction cache, and transmitting a read start instruction signal or a write start instruction si

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Han Jin Ho
• Kwon Young Su
• Shin Kyoung Seon

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title