Device and processing method

Patent metadata

Field	Value
Publication number	US-9824016-B2
Application number	US-201614992435-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Jan 14, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A device includes, a memory, and, a processor coupled to the memory, including a cache memory, and configured, to hold a memory access instruction for executing an access to the memory and a prefetch instruction for executing a prefetch to the memory, to determine whether or not data which is a subject data of the memory access instruction is held in the cache memory, and when the data is held in the cache memory and when a corresponding prefetch instruction that is a prefetch instruction corresponding to the memory access instruction is held in the processor, not to execute an execution of the corresponding prefetch instruction.

First claim

What is claimed is:

1. A device comprising:
a memory; and
a processor including a cache memory coupled to the memory, the processor configured to:
hold a memory access instruction to access the memory and a prefetch instruction to prefetch from the memory,
determine whether data which is a target of the memory access instruction is held in the cache memory, and
when the data is held in the cache memory and when a prefetch instruction corresponding to the memory access instruction is held in the processor, not execute the corresponding prefetch instruction.

2. The device according to claim 1 , wherein the processor is configured to:
add, to the memory access instruction and the prefetch instruction, identification information indicating a correspondence between the memory access instruction and the prefetch instruction,
hold the prefetch instruction with the identification information, and
when the data is held in the cache memory and when the corresponding prefetch instruction with the identification corresponding to the memory access instruction is held in the processor, not execute the corresponding prefetch instruction.

3. The device according to claim 1 , wherein the processor is configured to:
hold deterrence information indicating whether the prefetch instruction is valid or invalid with the prefetch instruction, and
set, if the corresponding prefetch instruction is held in the processor, the deterrence information to a state indicating the prefetch instruction is invalid.

4. The device according to claim 1 , wherein the processor is configured to:
hold history information indicating whether a cache hit or a cache miss has occurred for each of memory accesses in accordance with a plurality of memory access instructions,
generate an index based on a program counter value indicating an address of the cache memory in which the memory access instructions are stored and the history information,
hold prediction pattern information indicating frequency of the cache hit, and
output, based on the prediction pattern information, among pieces of the prediction pattern information that are held, which corresponds to the index generated using the program counter value of the memory access instruction that is a prediction target, prediction result information indicating whether the memory access instruction that is a prediction target is the target memory access instruction.

5. The device according to claim 1 , wherein the processor is configured to:
execute the memory access instruction and the prefetch instruction.

6. A processing method using a memory and a processor including a cache memory, the method comprising:
holding a memory access instruction to access the memory and a prefetch instruction to prefetch from the memory;
determining whether data which is a target of the memory access instruction is held in the cache memory; and
when the data is held in the cache memory and when a prefetch instruction corresponding to the memory access instruction is held in the processor, not executing the corresponding prefetch instruction.

7. The processing method according to claim 6 , further comprising:
adding, to the memory access instruction and the prefetch instruction, identification information indicating a correspondence between the memory access instruction and the prefetch instruction;
holding the prefetch instruction with the identification information; and
when the data is held in the cache memory and when the corresponding prefetch instruction with the identification corresponding to the memory access instruction is held in the processor, not executing the corresponding prefetch instruction.

8. The processing method according to claim 6 , further comprising:
holding deterrence information indicating whether the prefetch instruction is valid or invalid with the prefetch instruction; and
setting, if the corresponding prefetch instruction is held in the processor, deterrence information to a state indicating the prefetch instruction is invalid.

9. The processing method according to claim 6 , further comprising:
holding history information indicating whether a cache hit or a cache miss has occurred for each of memory accesses in accordance with a plurality of memory access instructions;
generating an index based on a program counter value indicating an address of the cache memory in which the memory access instructions are stored and the history information;
holding prediction pattern information indicating frequency of the cache hit; and
outputting, based on the prediction pattern information, among pieces of the prediction pattern information that are held, which corresponds to the index generated using the program counter value of the memory access instruction that is a prediction target, prediction result information indicating whether the memory access instruction that is a prediction target is the target memory access instruction.

10. The processing method according to claim 6 , further comprising:
executing the memory access instruction and the prefetch instruction.

Assignees

• Fujitsu Ltd

Inventors

• Kimura Shigeru

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title