Memory access by dual processor systems
US-2016154751-A1 · Jun 2, 2016 · US
Processor system, engine control system and control method
US9823957B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9823957-B2 |
| Application number | US-201514804970-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 21, 2015 |
| Priority date | Aug 19, 2014 |
| Publication date | Nov 21, 2017 |
| Grant date | Nov 21, 2017 |
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Abstract
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A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system.
First claim
Opening claim text (preview).
What is claimed is: 1. A processor system comprising: a master processor that successively processes a plurality of tasks; a checker processor that successively processes at least one of the plurality of tasks; and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not…
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- G06F11/079Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9823957B2 cover?
- A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation …
- Who is the assignee on this patent?
- Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F11/079. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).