System and method of reissue parking for a microprocessor

Patent metadata

Field	Value
Publication number	US-9823933-B2
Application number	US-201514659372-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Mar 9, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A reissue instruction parking system for a microprocessor including a reservation stations module that dispatches instructions for execution and a reorder buffer that reissues instructions to the reservation stations module during a reissue state, in which the reissue instruction parking system includes at least one first pipeline stage and at least one second pipeline stage, in which the first pipeline stages provide a first reissue instruction from a reissue data path to the reservation stations module during the reissue state and that parks the first reissue instruction once the reservation stations module is determined to be full, and in which the second pipeline stages select a pointer to the reorder buffer which provides a corresponding first reissue instruction onto the reissue data path, in which the second pipeline stages are placed into a hold state when a second full signal is asserted.

First claim

What is claimed is:

1. A reissue instruction parking system for a microprocessor, wherein the microprocessor includes a reservation stations module that dispatches instructions for execution and a reorder buffer that reissues instructions to the reservation stations module during a reissue state, said reissue instruction parking system comprising:
at least one first pipeline stage that provides a first reissue instruction from a reissue data path to the reservation stations module during the reissue state, and that parks said first reissue instruction when a first full signal is asserted, wherein said first full signal is asserted once the reservation stations module is determined to be full during the reissue state; and
at least one second pipeline stage that provides a pointer selected by the reorder buffer to the reorder buffer, in which the reorder buffer provides said first reissue instruction corresponding to said selected pointer onto said reissue data path, wherein said at least one second pipeline stage is placed into a hold state when a second full signal is asserted.

2. The reissue instruction parking system of claim 1 , wherein said second full signal is a latched version of said first full signal.

3. The reissue instruction parking system of claim 1 , wherein said at least one first pipeline stage further comprises:
reissue parking logic that parks said first reissue instruction when said first full signal is asserted, that selects a gated second reissue instruction registered from said reissue data path when said first full signal is negated and when said second full signal is asserted, and that selects a third reissue instruction from said reissue data path when said first and second full signals are both negated.

4. The reissue instruction parking system of claim 3 , wherein said reissue parking logic comprises:
a gating register that holds a second reissue instruction from said reissue data path upon assertion of said first full signal and that outputs said gated second reissue instruction; and
gating reissue select logic that selects said first reissue instruction when said first full signal is asserted, that selects said gated second reissue instruction when said first full signal is negated and when said second full signal is asserted, that selects said third reissue instruction from said reissue data path when said first and second full signals are both negated.

5. The reissue instruction parking system of claim 4 , wherein said reissue parking logic further comprises:
a primary register having an input coupling to said output of said gating reissue select logic and having an output providing said first reissue instruction to the reservation stations module.

6. The reissue instruction parking system of claim 1 , wherein said at least one first pipeline stage further comprises:
a primary register providing said first reissue instruction to the reservation stations module when said first full signal is negated, and holding said first reissue instruction from said reissue data path when said first full signal is asserted.

7. The reissue instruction parking system of claim 1 , wherein said at least one second pipeline stage comprises:
pointer hold register logic having an input coupled to said pointer selected by the reorder buffer and developing a hold pointer which is a latched version of said selected pointer, wherein said pointer hold register logic provides said selected pointer to the reorder buffer when said second full signal is negated, and provides said hold pointer to the reorder buffer when said second full signal is asserted.

8. The reissue instruction parking system of claim 1 , wherein said reservation stations module incorporates multiple reservation stations queues, and if any one of said reservation stations queues is full, said first full signal is asserted.

9. A microprocessor, comprising:
at least one execution unit;
a reservations station module that dispatches instructions for execution by said at least one execution unit;
a reorder buffer that reissues instructions to said reservation stations module during a reissue state; and
a reissue instruction parking system, comprising:
at least one first pipeline stage that provides a first reissue instruction from a reissue data path to the reservation stations module during the reissue state, and that parks said first reissue instruction when a first full signal is asserted, wherein said first full signal is asserted once the reservation stations module is determined to be full during the reissue state;
at least one second pipeline stage that provides a pointer selected by the reorder buffer to the reorder buffer, in which the reorder buffer provides said first reissue instruction corresponding to said selected pointer onto said reissue data path, wherein said at least one second pipeline stage is placed into a hold state when a second full signal is asserted; and
a reissue register having an input coupled to an output of said reorder buffer and having an output coupled to said reissue data path.

10. The microprocessor of claim 9 , wherein said second full signal is a latched version of said first full signal.

11. The microprocessor of claim 9 , wherein said at least one first pipeline stage further comprises:
reissue parking logic that parks said first reissue instruction when said first full signal is asserted, that selects a gated second reissue instruction registered from said reissue data path when said first full signal is negated and when said second full signal is asserted, and that selects a third reissue instruction from said reissue data path when said first and second full signals are both negated.

12. The microprocessor of claim 11 , wherein said reissue parking logic comprises:
a gating register that holds a second reissue instruction from said reissue data path upon assertion of said first full signal and that outputs said gated second reissue instruction; and
gating reissue select logic that selects said first reissue instruction when said first full signal is asserted, that selects said gated second reissue instruction when said first full signal is negated and when said second full signal is asserted, that selects said third reissue instruction from said reissue data path when said first and second full signals are both negated.

13. The microprocessor of claim 12 , wherein said reissue parking logic further comprises:
a primary register having an input coupling to said output of said gating reissue select logic and having an output providing said first reissue instruction to said reservation stations module.

14. The microprocessor of claim 9 , wherein said at least one first pipeline stage further comprises:
a primary register providing said first reissue instruction to the reservation stations module when said first full signal is negated, and holding said first reissue instruction from said reissue data path when said first full signal is asserted.

15. The microprocessor of claim 9 , wherein said at least one second pipeline stage comprises:
pointer hold register logic having an input coupled to said pointer selected by the reorder buffer and developing a hold pointer which is a latched version of said selected pointer, wherein said pointer hold register logic provides said selected pointer to the reorder buffer when said second full signal is negated, and provides said hold pointer to the reorder buffer when said second full signal is asserted.

16. A method of parking reissue instructions for a microprocessor, wherein the microprocessor includes a reservation stations m

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Zou Penghao
• Yang Mengchen
• Wang Jianbin
• Yu Xiaoyuan
• Gao xin yu

Classifications

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3855 Primary

  Physics · mapped topic

• G06F9/3856 Primary

  Reordering of instructions, e.g. using queues or age tags · CPC title