Controlling power delivery to a processor via a bypass

Patent metadata

Field	Value
Publication number	US-9823719-B2
Application number	US-201313906652-A
Country	US
Kind code	B2
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processor cores to operate at an independently controllable voltage and frequency;
a plurality of linear regulators to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of processor cores;
a plurality of selectors each coupled to an output of one of the plurality of linear regulators and one of the plurality of processor cores, each of the plurality of selectors to provide a regulated voltage from the one of the plurality of linear regulators or a bypass voltage to a corresponding one of the plurality of processor cores; and
a power control unit (PCU) to determine an operating voltage for the plurality of processor cores, the PCU including a bypass logic to determine whether the operating voltage for the plurality of processor cores is the same voltage or at least substantially the same voltage, and responsive to the determination to cause the plurality of selectors to provide the bypass voltage to the corresponding one of the plurality of processor cores and cause the plurality of linear regulators to be disabled.

2. The processor of claim 1 , wherein the PCU is to control each of the plurality of selectors based on a target operating point for the corresponding processor core.

3. The processor of claim 2 , wherein the PCU is to disable a first linear regulator when a first selector coupled to the first linear regulator is to provide the bypass voltage to a first processor core coupled to the first selector.

4. The processor of claim 1 , wherein the plurality of linear regulators are to receive the first voltage from a single voltage rail coupled to the processor.

5. The processor of claim 4 , wherein the bypass voltage corresponds to the first voltage.

6. The processor of claim 1 , wherein at least one of the plurality of linear regulators comprises:
a comparator to generate a comparison signal based on comparison of a reference voltage to the regulated voltage;
a control logic to receive the comparison signal and to generate at least one control signal based at least in part thereon; and
a plurality of power gates to receive the first voltage and to provide the regulated voltage responsive to the at least one control signal.

7. The processor of claim 6 , wherein the PCU is to provide a digital voltage value to the linear regulator and the linear regulator is to generate the reference voltage responsive thereto.

8. The processor of claim 1 , wherein the same voltage or the substantially same voltage is substantially equal to the first voltage.

9. The processor of claim 1 , wherein the PCU is to disable a first one of the plurality of linear regulators when a corresponding first one of the plurality of processor cores is to operate at a voltage at least substantially equal to the first voltage.

10. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving, in a power controller of a multicore processor, target operating point requests from a plurality of processor cores of the multicore processor;
responsive to the plurality of processor cores requesting the same or substantially the same operating voltage, providing a bypass voltage received via an external voltage rail to the plurality of processor cores by controlling a plurality of selectors to provide the bypass voltage to the plurality of processor cores;
disabling a plurality of linear regulators of the multicore processor; and
responsive to the plurality of processor cores not requesting the same or substantially the same operating voltage, controlling a first selector, coupled to receive the bypass voltage and a regulated voltage provided by a first one of the plurality of linear regulators, to provide the regulated voltage to a first core of the plurality of processor cores.

11. The non-transitory machine readable medium of claim 10 , wherein the method further comprises receiving platform configuration information including information regarding one or more external voltage rails coupled to the multicore processor in the power controller and mapping the one or more external voltage rails to a plurality of on-chip voltage rails.

12. The non-transitory machine readable medium of claim 10 , wherein the method further comprises responsive to the target operating point requests, determining a maximum operating voltage requested by the plurality of processor cores and communicating the maximum operating voltage to a platform power controller to cause a voltage rail coupled the platform power controller to provide the bypass voltage at the maximum operating voltage.

13. A system comprising:
a multicore processor including a plurality of processor cores to operate at an independently controllable voltage and frequency, a plurality of linear regulators to receive a first voltage and output a regulated voltage, a plurality of multiplexers each coupled to an output of one of the plurality of linear regulators and to one of the plurality of processor cores, each of the plurality of multiplexers to provide a regulated voltage from one of the plurality of linear regulators or an external voltage to the corresponding one of the plurality of processor cores, and a power control unit (PCU) to control each of the plurality of multiplexers based at least in part on a target operating point for the corresponding processor core, wherein the PCU is to determine whether the target operating point for the plurality of processor cores is the same voltage or at least substantially the same voltage, and responsive to the determination to cause the plurality of multiplexers to provide the external voltage to the corresponding one of the plurality of processor cores and cause the plurality of linear regulators to be disabled; and
a power management controller coupled to the multicore processor, the power management controller to provide the external voltage to the multicore processor via at least one external voltage rail.

14. The system of claim 13 , wherein the PCU is coupled to the power management controller to provide a voltage identification value to the power management controller, wherein the power management controller is to provide the external voltage based at least in part on the voltage identification value.

15. The system of claim 14 , wherein the PCU is to provide the voltage identification value to a first linear regulator of the plurality of linear regulators, the first linear regulator comprising:
a comparator to generate a comparison signal based on comparison of a reference voltage to the regulated voltage, a control logic to receive the comparison signal and to generate at least one control signal based at least in part thereon, and a plurality of power gates to receive the external voltage and to provide the regulated voltage responsive to the at least one control signal.

16. The system of claim 15 , wherein the PCU is to disable the first linear regulator when a first processor core coupled to the first linear regulator is to receive the external voltage.

17. The system of claim 16 , wherein the PCU is to disable the first linear regulator when the first processor core is to operate at a voltage at least substantially equal to the external voltage.

18. The system of claim 13 , wherein the power management controller is coupled to the multicore processor via a single external voltage rail and the multicore processor comprises a plurality of internal vo

Assignees

• Intel Corp

Inventors

• Jahagirdar Sanjeev S
• Damaraju Satish K
• Chen Yun-Han
• Wells Ryan D
• Sodhi Inder M
• Sarurkar Vishram
• Drottar Ken
• Choubal Ashish V
• Islam Rabiul

Classifications

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic