Built-in self test system, system on a chip and method for controlling built-in self tests

Patent metadata

Field	Value
Publication number	US-9823296-B2
Application number	US-201214402949-A
Country	US
Kind code	B2
Filing date	Jun 7, 2012
Priority date	Jun 7, 2012
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

First claim

The invention claimed is:

1. A built-in self test system, comprising:
an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry;
a low power control unit operable to switch said integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering said low power mode;
a built-in self test control unit coupled to said built-in self test circuitry and said low power control unit and arranged to initiate a built-in self test when receiving said BIST wake-up signal; and
a self test supervision unit connected to said low power control unit and comprising a process safety timer, wherein said low power control unit is arranged to provide a trigger signal to said process safety timer of said self test supervision unit when switching said integrated circuit device into said low power mode.

2. The built-in self test system as claimed in claim 1 , wherein said self test supervision unit is arranged to provide a process safety timer expiration trigger signal to said low power control unit on expiration of said process safety timer.

3. The built-in self test system as claimed in claim 2 , wherein said low power control unit is arranged to generate said BIST wake-up signal depending on said process safety timer expiration trigger signal.

4. The built-in self test system as claimed in claim 1 , wherein said self test supervision unit is arranged to provide said process safety timer expiration trigger signal to said built-in self test control unit.

5. A system on a chip, comprising a built-in self test system as claimed in claim 1 .

6. A built-in self test system, comprising:
an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry;
a low power control unit operable to switch said integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering said low power mode; and
a built-in self test control unit coupled to said built-in self test circuitry and said low power control unit and arranged to initiate a built-in self test when receiving said BIST wake-up signal, wherein said built-in self test circuitry is comprised in a plurality of BIST regions independently testable by said built-in self test unit, and wherein said self test supervision unit is arranged to provide a selection signal to said built-in self test unit for selecting a next BIST region for test.

7. The built-in self test system as claimed in claim 6 wherein said built-in self test control unit is arranged to initiate a different built-in self test for at least some of said plurality of BIST regions.

8. The built-in self test system as claimed in claim 6 wherein said integrated circuit device comprises a plurality of power domains.

9. The built-in self test system as claimed in claim 8 wherein each of said plurality of BIST regions is aligned with a single one of said plurality of power domains.

10. The built-in self test system as claimed in claim 6 wherein at least one of said plurality of BIST regions is arranged to selectively receive power during low power mode.

11. A system on a chip, comprising a built-in self test system as claimed in claim 6 .

12. A built-in self test system, comprising:
an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry;
a low power control unit operable to switch said integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering said low power mode;
a built-in self test control unit coupled to said built-in self test circuitry and said low power control unit and arranged to initiate a built-in self test when receiving said BIST wake-up signal; and
a BIST result accumulation unit arranged to receive BIST result signatures provided by said built-in self test control unit and to accumulate at least some of said BIST result signatures to generate at least one accumulated BIST result signature, wherein said BIST result accumulation unit is arranged to compare said at least one accumulated BIST result signature with a pre-defined BIST signature.

13. A system on a chip, comprising a built-in self test system as claimed in claim 12 .

14. A built-in self test system, comprising:
an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry;
a low power control unit operable to switch said integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering said low power mode; and
a built-in self test control unit coupled to said built-in self test circuitry and said low power control unit and arranged to initiate a built-in self test when receiving said BIST wake-up signal, wherein said BIST wake-up signal is received periodically with a period different from a duration of a wake-up cycle of said integrated circuit device.

15. A system on a chip, comprising a built-in self test system as claimed in claim 14 .

16. A method for controlling built-in self tests of an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry, said method comprising:
switching said integrated circuit device into a low power mode;
generating a BIST wake-up signal during or before entering said low power mode;
initiating a built-in self test when receiving said BIST wake-up signal, and
providing a trigger signal to a process safety timer when switching said integrated circuit device into said low power mode and generating said BIST wake-up signal depending on an expiration of said process safety timer.

Assignees

• Thanner Manfred
• Culshaw Carl
• Frank Juergen
• Staudenmaier Michael
• Nxp Usa Inc

Inventors

• Thanner Manfred
• Culshaw Carl
• Frank Juergen
• Staudenmaier Michael

Classifications

• G01R31/31701 Primary

  Arrangements for setting the Unit Under Test [UUT] in a test mode · CPC title

• G01R31/2856 Primary

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title