Semiconductor device and method of testing semiconductor device

Patent metadata

Field	Value
Publication number	US-9823291-B2
Application number	US-201514810831-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Aug 11, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of semiconductor chips; and
a connecting portion that connects a plurality of terminals formed on one of the plurality of semiconductor chips with a plurality of terminals formed on another of the plurality of semiconductor chips,
wherein the plurality of terminals of each of the plurality of semiconductor chips is classified into a first group and a second group such that each of the plurality of terminals of each of the plurality of semiconductor chips belongs to either one of the first group or the second group to be controlled independently,
terminals in the first and second groups are arranged such that terminals belonging to the first group and terminals belonging to the second group are alternately arranged in a lateral direction as well as a longitudinal direction, and an interval between two terminals of a same group is larger than a predetermined interval
between terminals from each of the first and second groups adjacent with each other, and
each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals per each of the first group and the second group such that the terminals in each of the first group and the second group are controlled independently by a different selecting portion.

2. The semiconductor device according to claim 1 , wherein the plurality of terminals of each of the plurality of semiconductor chips is classified into the first group, the second group, and a third group each controlled with an independent control circuit such that each of the plurality of terminals of each of the plurality of semiconductor chips belongs to one of the first group, the second group, or the third group,
an interval between a third terminal of the third group and a second terminal of the second group adjacent to the third terminal is the predetermined interval, and
two third terminals of the third group adjacent with each other are arranged at an interval larger than the predetermined interval.

3. A method of testing a semiconductor device including a plurality of semiconductor chips and a connecting portion that connects a plurality of terminals formed on one of the plurality of semiconductor chips with a plurality of terminals formed on another of the plurality of semiconductor chips,
the testing method comprising:
dividing the plurality of terminals of each of the plurality of semiconductor chips into a first group and a second group such that each of the plurality of terminals of each of the plurality of semiconductor chips belongs to either one of the first group and the second group to be controlled independently;
arranging the terminals in the first group and the second group such that terminals belonging to the first group and terminals belonging to the second group are alternately arranged in a lateral direction as well as a longitudinal direction, and an interval between two terminals of a same group is larger than a predetermined interval between terminals from each of the first and second groups adjacent with each other;
testing a signal path including terminals connected to each other by the connecting portion, using a testing device for testing the semiconductor device; and
selecting a signal transmitting terminal among the plurality of terminals per each of the first group and the second group such that the terminals in each of the first group and the second group are controlled independently from each other using a selecting portion included in each of the first group and the second group, based on a test result from the testing the signal path.

4. The method according to claim 3 , wherein
the testing device selects the first group to be tested, and executes a first test of transmitting data of a first level and data of a second level different from the first level to a signal path corresponding to the first group to be tested and a signal path corresponding to the second group other than the first group to be tested, respectively, and a second test of transmitting the data of the second level and the data of the first level to the signal path corresponding to the first group to be tested and the signal path corresponding to second group other than the first group to be tested, respectively, and the selecting portion selects the signal transmitting terminal among the plurality of terminals per each of the first group and the second group, based on results of the first and second tests.

5. The semiconductor device according to claim 1 , wherein the connecting portion is formed with a plurality of bumps.

Assignees

• Fujitsu Ltd

Inventors

• Shikibu Takahiro
• Nakada Tatsumi

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/722

  between stacked chips · CPC title