Printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9820378-B2
Application number	US-201615241714-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Aug 19, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Disclosed are a printed circuit board and a method of manufacturing the printed circuit board. The printed circuit board includes an insulating layer, and a circuit pattern formed on the insulating layer, wherein the circuit pattern includes a first circuit pattern formed on the insulating layer and including a corner portion of an upper portion which has a predetermined curvature and a second circuit pattern formed on the first circuit pattern and configured to cover an upper surface of the first circuit pattern including the corner portion.

First claim

What is claimed is:

1. A printed circuit board comprising:
an insulating layer;
a plating seed layer disposed on the insulating layer and formed of copper (Cu);
a circuit pattern disposed on the plating seed layer; and
a top metal layer disposed on the circuit pattern,
wherein the circuit pattern comprises:
a first circuit pattern disposed on the plating seed layer and formed of copper (Cu), and
a second circuit pattern disposed on the first circuit pattern and formed of copper (Cu),
wherein a thickness of the second circuit pattern is thinner than a thickness of the first circuit pattern,
wherein the top metal layer is formed of gold (Au),
wherein a width of a lower surface of the top metal layer is wider than a width of an upper surface of the second circuit pattern,
wherein a first part of a lower surface of the second circuit pattern is positioned at a lower level than a first part of an upper surface of the first circuit pattern,
wherein the first part of the lower surface of the second circuit pattern is in direct physical contact with the first circuit pattern, and
wherein the lower surface of the top metal layer comprises: a first portion in contact with the upper surface of the second circuit pattern; and a second portion spaced apart from the plating seed layer, the first circuit pattern, and the second circuit pattern by respective predetermined distances.

2. The printed board of claim 1 , wherein a length of the second portion of the top metal layer is in a range from 3 μm to 7 μm.

3. The printed board of claim 1 , wherein the lower surface of the top metal layer has a wider width than a width of the plating seed layer.

4. The printed board of claim 1 , wherein the lower surface of the top metal layer has a wider width than a width of the first circuit pattern.

5. The printed board of claim 1 , wherein a thickness of the second circuit pattern is in a range from 1 μm to 13 μm.

6. The printed board of claim 1 , wherein a thickness of the second circuit pattern is in a range from 3 μm to 10 μm.

7. The printed board of claim 1 , wherein a thickness of the second circuit pattern is in a range from 3 μm to 6 μm.

8. The printed board of claim 1 , wherein a lower surface of the second circuit pattern has a longer length than a lower surface of the plating seed layer.

9. A printed circuit board comprising:
an insulating layer,
a plating seed layer disposed on the insulating layer;
a first circuit pattern disposed on the plating seed layer and directly contacted with the plating seed layer;
a second circuit pattern directly contacted with the first circuit pattern and formed of copper; and
a top metal layer directly contacted with the second circuit pattern and formed of gold (Au),
wherein the top metal layer has a wider width than a width of the second circuit pattern,
wherein the plating seed layer and the first circuit pattern are formed of copper (Cu),
wherein a thickness of the second circuit pattern is thinner than a thickness of the first circuit pattern,
wherein a first part of a lower surface of the second circuit pattern is positioned at a lower level than a first part of an upper surface of the first circuit pattern,
wherein the first part of the lower surface of the second circuit pattern is in direct physical contact with the first circuit pattern, and
wherein the lower surface of the top metal layer comprises: a first portion in contact with the upper surface of the second circuit pattern; and a second portion spaced apart from the plating seed layer, the first circuit pattern, and the second circuit pattern by respective predetermined distances.

10. The printed board of claim 9 , wherein a length of the second portion of the top metal layer is in a range from 3 μm to 7 μm.

11. The printed board of claim 9 , wherein a width of a lower surface of the top metal layer is wider than a width of an upper surface of the second circuit pattern.

12. The printed board of claim 9 , wherein a thickness of the second circuit pattern is in a range from 1 μm to 13 μm.

13. The printed board of claim 9 , wherein a plurality of the first circuit patterns are disposed on the plating seed layer, and a plurality of the second circuit patterns are disposed on the plurality of the first circuit patterns.

14. The printed board of claim 9 , wherein roughness is introduced to an upper surface of the insulating layer.

15. The printed board of claim 9 , wherein the insulating layer includes at least one of a thermosetting polymer, a thermoplastic polymer, a ceramic, an organic-inorganic composition material, a fiberglass immersion, an epoxy-based insulating resin, and a polyimide-based resin.

Assignees

• Lg Innotek Co Ltd

Inventors

• Hwang Jung Ho
• Lee Han Su
• Choi Dae Young
• Kwon Soon Gyu
• Jeong Dong Hun
• Jeong In Ho
• Son Kil Dong
• Kim Sang Hwa
• Lee Sang Young
• Jeon Jae Hoon
• Lee Jin Hak
• Bae Yun Mi

Classifications

• H05K2203/1184

  Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching · CPC title

• H05K2203/0588

  Second resist used as pattern over first resist · CPC title

• H05K2201/0347

  Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias · CPC title

• H05K3/244

  Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465) · CPC title

• H05K3/108 Primary

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title