System and method for synchronous processing of analog and digital pathways in a digital radio receiver

Patent metadata

Field	Value
Publication number	US-9819480-B2
Application number	US-201514817578-A
Country	US
Kind code	B2
Filing date	Aug 4, 2015
Priority date	Aug 4, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of processing a digital radio broadcast signal in a digital radio receiver includes: receiving baseband signal samples at a first sample rate; adjusting the sample rate of the baseband signals based on a difference between a receiver clock and a transmitter clock to produce adjusted baseband signal samples at a second sample rate; filtering the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples, wherein the digital component and the analog component are synchronous; and separately demodulating the digital component and the analog component to produce a digital output signal and an analog output signal. A receiver that uses the method is also provided.

First claim

What is claimed is:

1. A method of processing a digital radio broadcast signal in a digital radio receiver comprising:
receiving baseband signal samples at a first sample rate;
using an asynchronous sample rate converter to adjust the sample rate of the baseband signal samples based on a sample rate correction value derived from both a sample slip and a sample rate offset between a receiver and a transmitter to produce adjusted baseband signal samples at a second sample rate to drive both the sample slip and the sample rate offset to zero;
filtering the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples, wherein the digital component and the analog component are synchronous; and
separately demodulating the digital component and the analog component to produce a digital output signal and an analog output signal.

2. The method of claim 1 , wherein the step of using an asynchronous sample rate converter to adjust the sample rate of the baseband signal samples further comprises:
resampling the baseband signal samples using the asynchronous sample rate converter.

3. The method of claim 1 , further comprising:
using a Kalman filter to estimate the sample slip and the sample rate offset.

4. The method of claim 3 , wherein a linear quadratic regulator (LQR) algorithm is used to determine the correction value.

5. The method of claim 1 , wherein the step of filtering the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples is implemented in an isolation filter.

6. The method of claim 1 , further comprising:
using a symbol time adjustment module during an initial phase of tracking to drive the sample slip toward zero.

7. The method of claim 6 , wherein:
the symbol time adjustment module adjusts samples of only the digital component.

8. The method of claim 1 , further comprising:
detecting a loss of the digital radio broadcast signal;
stopping the step adjusting the sample rate of the baseband signal samples;
detecting a come back of the digital radio broadcast signal; and
restarting the step adjusting the sample rate of the baseband signal samples using a reset tracking algorithm.

9. A receiver for processing a digital radio broadcast signal, the receiver comprising;
a processing system including an asynchronous sample rate converter, an isolation filter, an OFDM demodulator, and an analog demodulator configured to receive baseband signal samples at a first sample rate; adjust the sample rate of the baseband signal samples based on a sample rate correction value derived from both a sample slip and a sample rate offset between a receiver and a transmitter to produce adjusted baseband signal samples at a second sample rate and to drive both the sample slip and the sample rate offset to zero; filter the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples, wherein the digital component and the analog component are synchronous; and separately demodulate the digital component and the analog component to produce a digital output signal and an analog output signal.

10. The receiver of claim 9 , wherein the processing system is further configured for adjusting the sample rate of the baseband signal samples including resampling the baseband signal samples.

11. The receiver of claim 10 , wherein the processing system uses a Kalman filter to estimate the sample slip and the sample rate offset.

12. The receiver of claim 11 , wherein the processing system uses a linear quadratic regulator (LQR) algorithm to determine the correction value.

13. The receiver of claim 9 , wherein the processing system further comprises a symbol time adjustment module configured to drive the sample slip toward zero during an initial phase of tracking.

14. The receiver of claim 13 , wherein the symbol time adjustment module adjusts samples of only the digital component.

15. An article of manufacture comprising a computer readable storage medium containing executable instructions adapted to a cause a processing system to execute the method of claim 1 .

Assignees

• Ibiquity Digital Corp

Inventors

• Nekhamkin Michael
• Chen Hangjun
• Li Linlin

Classifications

• H04W56/005

  compensating for timing error by adjustment in the receiver · CPC title

• H04L27/2662

  Symbol synchronisation · CPC title

• H04L27/2647

  Arrangements specific to the receiver only (equalisation H04L27/01) · CPC title

• H04L7/0079

  Receiver details · CPC title

• H04L7/0041 Primary

  Delay of data signal · CPC title