Injection locked ring oscillator based digital-to-time converter and method for providing a filtered interpolated phase signal

Patent metadata

Field	Value
Publication number	US-9819356-B2
Application number	US-201414570299-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

First claim

What is claimed is:

1. A digital-to-time-converter (DTC) comprising:
a phase interpolator configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal; and
a ring oscillator configured to receive the interpolated output phase signal, to lock on to a frequency and a phase of the interpolated output phase signal and to provide a filtered phase signal having transitions separated in time in accordance with corresponding transitions of the digital representations of the two or more distinct phase signals;
wherein the phase interpolator is configured to receive a plurality of coefficients, and to interpolate the two or more distinct phase signals using the plurality of coefficients to provide the interpolated output phase signal; and
wherein the phase interpolator includes two or more digital-to-analog converters (DACs), each DAC of the two or more DACs is configured to receive a corresponding digital representation of one phase signal of the two or more distinct phase signals, to receive a coefficient of the plurality of coefficients, and to provide an analog representation of the one phase signal.

2. The DTC of claim 1 , wherein the phase interpolator includes a summer coupled to an output of each of the two or more DACs, the summer configured to sum the analog representation of the one phase signal of each of the two or more DACs and to provide the interpolated output phase signal.

3. The DIC of claim 1 , wherein the analog representation of the one phase signal is a current signal.

4. The DTC of claim 1 , wherein the analog representation of the one phase signal is a charge signal.

5. The DTC of claim 1 , including a plurality of frequency dividers configured to receive reference frequency and phase information of a reference signal and to provide the digital representations of the two or more distinct phase signals using the reference frequency and phase information of the reference signal.

6. The DTC of claim 5 , including a phase lock loop configured to provide the reference frequency and phase information to each of the plurality of frequency dividers.

7. The DTC of claim 1 , wherein the phase interpolator is configured to receive digital representations three or more distinct phase signals, and to interpolate the digital representations of the three or more distinct phase signals to provide the interpolated output phase signal.

8. The DTC of claim 1 , wherein each of the digital representations of three distinct phase signals include a common fundamental frequency.

9. A method of providing a filtered interpolated phase signal, the method comprising:
receiving digital representations of two or more distinct phase signals at a phase interpolator for a digital-to-time converter (DTC);
receiving a plurality of coefficients at the phase interpolator;
interpolating the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal using the phase interpolator;
injecting the interpolated output phase signal into a ring oscillator;
locking onto a frequency and a phase of the interpolated output phase signal;
providing a filtered interpolated phase signal at an output of the ring oscillator;
wherein interpolating the digital representations of the two or more distinct phase signals includes interpolating the digital representations of the two or more distinct phase signals using the plurality of coefficients to provide the interpolated output phase signal;
wherein receiving the digital representations of the two or more distinct phase signals at the phase interpolator includes receiving a digital representation of one phase signal of the two or more distinct phase signals at a first corresponding digital-to-analog converter (DAC) of the phase interpolator, wherein the first corresponding DAC is one of two or more DACs of the phase interpolator; and
wherein receiving a plurality of coefficients at the phase interpolator includes receiving one coefficient of the plurality of coefficients at the first corresponding DAC.

10. The method of claim 9 , including providing an analog representation of the one phase signal using the first corresponding DAC and the one coefficient.

11. The method of claim 10 , including summing each output of the two or more DACs to provide the interpolated output phase signal.

12. The method of claim 10 , wherein providing the analog representation of the one phase signal includes providing an analog current signal representative of the one phase signal.

13. The method of claim 10 , wherein providing the analog representation of the one phase signal includes providing an analog charge signal representative of the one phase signal.

14. The method of claim 9 , including receiving reference frequency and phase information of a reference signal at a plurality of frequency dividers; and
providing the digital representations of the three distinct phase signals using the plurality of frequency dividers and the reference frequency and phase information of the reference signal.

15. The method of claim 14 , including providing the reference frequency and phase information to each of the plurality of frequency dividers using a phase lock loop (PLL).

16. The method of claim 14 , wherein each of the digital representations of the three distinct phase signals includes a common fundamental frequency.

17. A transceiver comprising:
a baseband processor configured to provide phase modulation information;
a reference generator configured to provide two or more reference phase signals, each of the two or more reference phase signals having a phase offset from a phase of each of the other reference phase signals; and
a digital-to-time converter, the digital to time converter comprising:
a phase interpolator configured to receive the two or more reference phase signals and the phase modulation information, and to interpolate the two or more reference phase signals to provide an interpolated output phase signal;
a ring oscillator configured to receive the interpolated output phase signal, to lock on to a frequency and a phase of the interpolated output phase signal and to provide a filtered phase signal;
wherein the phase interpolator is configured to receive a plurality of coefficients, and to interpolate the two or more distinct phase signals using the plurality of coefficients to provide the interpolated output phase signal; and
wherein the phase interpolator includes two or more digital-to-analog converters (DACs), each DAC of the two or more DACs is configured to receive a corresponding digital representation of one phase signal of the two or more distinct phase signals, to receive a coefficient of the plurality of coefficients, and to provide an analog representation of the one phase signal.

18. The transceiver of claim 17 , further comprising an amplifier configured to receive the filtered phase signal and a corresponding amplitude signal and to provide a radio frequency signal.

19. The transceiver of claim 18 , further comprising a demodulator configured to receive a radio frequency signal from an antenna and the filtered phase signal and to provide a data signal representative of data demodulated from the radio signal using the filtered phase signal.

20. The transceiver of claim 18 , further comprising one or more antenna coupled to the amplifier.

Assignees

• Intel Ip Corp

Inventors

• Ponton Davide
• Passamani Antonio
• Bevilacqua Andrea

Classifications

• H03L7/0998

  using phase interpolation · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03M1/662 Primary

  Multiplexed conversion systems · CPC title

• H03M1/82

  with intermediate conversion to time interval · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title