Method and circuit for reducing collector-emitter voltage overshoot in an insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-9819339-B2
Application number	US-201514710989-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	May 13, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A circuit for reducing collector-emitter voltage (V CE ) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the V CE overshoot. The circuitry is further operable to combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse. A corresponding method of reducing V CE overshoot in an IGBT also is provided.

First claim

What is claimed is:

1. A circuit, comprising:
an insulated gate bipolar transistor (IGBT) operable to conduct current in a first phase of a switching cycle and block current in a second phase of the switching cycle responsive to a control signal applied to the gate of the IGBT, wherein overshoot occurs in the collector-emitter voltage (V CE ) of the IGBT in the second phase of the switching cycle; and
circuitry operable to:
generate a pulse which has a rising edge synchronized to the moment when current through the IGBT begins to fall in the second phase of the switching cycle and a width which is a fraction of a duration of the V CE overshoot; and
combine the pulse with the control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT in the second phase of the switching cycle to above a threshold voltage of the IGBT for the duration of the pulse.

2. The circuit of claim 1 , wherein the IGBT is a trench-gate IGBT.

3. The circuit of claim 1 , wherein the pulse has a fixed amplitude.

4. The circuit of claim 1 , wherein the width of the pulse is fixed.

5. The circuit of claim 1 , wherein the width of the pulse is a function of an intrinsic turn-off fall time of the IGBT.

6. The circuit of claim 1 , wherein the width of the pulse is between ½ and ¼ the duration of the V CE overshoot.

7. The circuit of claim 1 , wherein the circuitry comprises:
a first circuit operable to sense collector or emitter current of the IGBT;
a second circuit operable to output a signal which represents the time-differentiation of the sensed collector or emitter current;
a third circuit operable to generate the pulse responsive to the signal output by the second circuit; and
a fourth circuit operable to combine the pulse and the control signal.

8. The circuit of claim 7 , wherein the third circuit has user-controllable amplitude gain and time constant variables for adjusting the amplitude and time duration of the pulse.

9. The circuit of claim 7 , wherein the third circuit is operable to adjust the width of the pulse responsive to a user input signal.

10. The circuit of claim 7 , wherein the fourth circuit is operable to pass the control signal uncombined with the pulse to the IGBT responsive to a pulse enable signal being deactivate.

11. The circuit of claim 7 , wherein the first circuit is operable to sense the collector or emitter current of the IGBT by sensing current through one of stray emitter inductance at an emitter terminal of the IGBT or a shunt resistor connected to the emitter terminal, and wherein the second circuit is operable to output the signal which represents the time-differentiation of the sensed collector or emitter current output based on one of the voltage across the stray emitter inductance, the voltage across the shunt resistor, a voltage induced at a Rogoswki coil magnetically coupled to the emitter terminal, or a voltage induced at a current transformer coil magnetically coupled to the emitter terminal.

12. The circuit of claim 11 , wherein the third circuit is operable to generate the pulse at the moment when the voltage measured by the second circuit begins to rise in the second phase of the switching cycle.

13. The circuit of claim 11 , wherein the third circuit comprises:
a protection circuit operable to clamp the output of the second circuit against excessively high voltage during short circuit turn-off;
a signal amplifier operable to amplify the protection circuit output; and
a first pulse generator operable to trigger responsive to a falling/rising edge of the signal amplifier output.

14. The circuit of claim 13 , wherein the third circuit further comprises a second pulse generator triggered by the same signal amplifier as the first pulse generator and operable to generate an additional pulse having a longer width than the pulse generated by the first pulse generator, and wherein the second pulse generator is enabled during short-circuit protection of the IGBT and disabled during normal operation of the IGBT.

15. The circuit of claim 14 , wherein the fourth circuit is operable to combine the pulses output by the first and the second pulse generators and the control signal.

16. The circuit of claim 14 , wherein the first and the second pulse generators each comprise a monostable multivibrator.

17. The circuit of claim 7 , wherein the third circuit has an input signal range which ranges from 0.1 to 2.0 times a nominal collector current of the IGBT during normal operation of the IGBT and ranges from 0.1 to 6.0 times the nominal collector current during short-circuit protection of the IGBT.

18. The circuit of claim 1 , wherein the circuitry is configured to disable generation of the pulse responsive to a command signal indicating the pulse is to be disabled.

19. The circuit of claim 1 , wherein the circuitry is configured to increase the width of the pulse in response to a signal which indicates a short-circuit fault condition such that the pulse width is narrower for normal operation and wider for short-circuit operation.

20. A method of reducing overshoot for an insulated gate bipolar transistor (IGBT) operable to conduct current in a first phase of a switching cycle and block current in a second phase of the switching cycle responsive to a control signal applied to the gate of the IGBT, the overshoot occurring in the collector-emitter voltage (V CE ) of the IGBT in the second phase of the switching cycle, the method comprising:
generating a pulse which has a rising edge synchronized to the moment when current through the IGBT begins to fall in the second phase of the switching cycle and a width which is a fraction of a duration of the V CE overshoot; and
combining the pulse with the control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT in the second phase of the switching cycle to above a threshold voltage of the IGBT for the duration of the pulse.

21. A circuit for reducing collector-emitter voltage (V CE ) overshoot in an insulated gate bipolar transistor (IGBT), the circuit comprising circuitry operable to:
generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the V CE overshoot; and
combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Ma Kwok Wai
• Cheung Sui Pung

Classifications

• H03K17/0406

  in composite switches · CPC title

• H03K17/168 Primary

  in composite switches · CPC title

• H03K17/08116

  in composite switches (H03K17/0812, H03K17/0814 take precedence) · CPC title