Power circuit and power module using MISFET having control circuit disposed between gate and source

Patent metadata

Field	Value
Publication number	US-9819338-B2
Application number	US-201615192677-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Dec 26, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q 1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q 4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG 1 ) connected between a first gate G 1 and a first source S 1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.

First claim

What is claimed is:

1. A power circuit comprising:
a main substrate;
a first electrode pattern disposed on the main substrate, the first electrode pattern is electrically connected to a positive-side power terminal;
a second electrode pattern disposed on the main substrate, the second electrode pattern is electrically connected to a negative-side power terminal;
a third electrode pattern disposed on the main substrate, the third electrode pattern is electrically connected to an output terminal;
a first MISFET in which a first drain is disposed on the first electrode pattern;
a second MISFET in which a second drain is disposed on the third electrode pattern; and
a first control circuit electrically connected between a first gate and a first source of the first MISFET, the first control circuit configured to control a current path conducted from the first source towards the first gate, wherein
the first MISFET includes a plurality of semiconductor chips, and the first control circuit is electrically connected to each of the semiconductor chips of the first MISFET.

2. The power circuit according to claim 1 , further comprising:
a second control circuit electrically connected between a second gate and a second source of the second MISFET, the second control circuit configured to control a current path conducted from the second source towards the second gate.

3. The power circuit according to claim 1 , wherein
the first control circuit comprises a first gated diode of which a first cathode is electrically connected to the first gate and a first anode is electrically connected to the first source.

4. The power circuit according to claim 2 , wherein
the second control circuit comprises a second gated diode of which a second cathode is electrically connected to the second gate, and a second anode is electrically connected to the second source.

5. The power circuit according to claim 1 , wherein
the first control circuit comprises a third MISFET of which a third drain is electrically connected to the first gate, and a third source is electrically connected to the first source.

6. The power circuit according to claim 2 , wherein
the second control circuit comprises a fourth MISFET of which a fourth drain is electrically connected to the second gate, and a fourth source is electrically connected to the second source.

7. The power circuit according to claim 1 , further comprising:
a signal wiring pattern for the first gate disposed on the main substrate, the signal wiring pattern for the first gate is electrically connected to the first gate; and
a first signal substrate in which a signal wiring pattern for a first source sense electrically connected to the first source is mounted.

8. The power circuit according to claim 2 , further comprising:
a signal wiring pattern for the second gate disposed on the main substrate, the signal wiring pattern for the second gate is electrically connected to the second gate; and
a second signal substrate in which a signal wiring pattern for a second source sense electrically connected to the second source is mounted.

9. The power circuit according to claim 7 , wherein
the first control circuit comprises a first gated diode electrically connected between the signal wiring pattern for the first gate and the signal wiring pattern for the first source sense.

10. The power circuit according to claim 8 , wherein
the second control circuit comprises a second gated diode electrically connected between the signal wiring pattern for the second gate and the signal wiring pattern for the second source sense.

11. The power circuit according to claim 7 , wherein
the first control circuit comprises a third MISFET electrically connected between the signal wiring pattern for the first gate and the signal wiring pattern for the first source sense.

12. The power circuit according to claim 8 , wherein
the second control circuit comprises a fourth MISFET electrically connected between the signal wiring pattern for the second gate and the signal wiring pattern for the second source sense.

13. The power circuit according to claim 11 , wherein
the power circuit further comprises a first gate capacitor for applying gate-negative bias, the first gate capacitor is electrically connected between a source of the third MISFET and a source sense of the first MISFET.

14. The power circuit according to claim 12 , wherein
the power circuit further comprises a second gate capacitor for applying gate-negative bias, the second gate capacitor is electrically connected between a source of the fourth MISFET and a source sense of the second MISFET.

15. The power circuit according to claim 3 , wherein
a circuit constant is set up so that a forward voltage when the first gated diode is conducting becomes lower than a negative-side absolute maximum rating of a voltage between the first gate and the first source in the first MISFET.

16. The power circuit according to claim 4 , wherein
a circuit constant is set up so that a forward voltage when the second gated diode is conducting becomes lower than a negative-side absolute maximum rating of a voltage between the second gate and the second source in the second MISFET.

17. The power circuit according to claim 15 , wherein
the first gated diode is a diode selected from the group consisting of a Zener diode and a Schottky barrier diode.

18. The power circuit according to claim 16 , wherein
the second gated diode is a diode selected from the group consisting of a Zener diode and a Schottky barrier diode.

19. The power circuit according to claim 7 , further comprising:
a shield for shielding a radiation noise between an inside of the first signal substrate or the main substrate, and the first signal substrate.

20. The power circuit according to claim 8 , comprising:
a shield for shielding a radiation noise between an inside of the second signal substrate or the main substrate, and the second signal substrate.

21. The power circuit according to claim 1 , wherein
one selected from the group consisting of the first MISFET and the second MISFET comprises an SiC MISFET.

22. The power circuit according to claim 1 , wherein
one selected from the group consisting of the first MISFET and the second MISFET comprises an SiC Trench MISFET.

23. The power circuit according to claim 2 , wherein
the second MISFET includes a plurality of semiconductor chips, and the second control circuit is electrically connected to each of the semiconductor chips of the second MISFET.

24. The power circuit according to claim 1 , further comprising
a snubber capacitor electrically connected between the first electrode pattern and the second electrode pattern.

25. The power circuit according to claim 3 , wherein
the first gated diode is disposed closer to a semiconductor chip side than to a mounting position of a signal terminal for external extraction on the main substrate.

26. The power circuit according to claim 9 , wherein
the first gated diode is disposed closer to a semiconductor chip side than to a mounting position of a signal terminal for external extraction on the main substrate.

27. The power circuit according to claim 1 , wherein
the positive-side power terminal and the negative-side power terminal are disposed at a first side of the main substrate, the output terminal is disposed at a second side of th

Assignees

• Rohm Co Ltd

Inventors

• Otake Hirotaka
• Yanagi Tatsuya
• Nakakohara Yusuke

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title