Time delay filters

Patent metadata

Field	Value
Publication number	US-9819325-B2
Application number	US-201615382335-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A time delay filter comprising a substrate comprising a first surface and a second surface opposite the first surface; a first LC resonator coupled to the substrate and comprising a first coupling point, a first capacitive element electrically coupled between the first coupling point and the first conductive region, and a first inductive element coupled between the first coupling point and the first conductive region, and comprising a first and second inductor tap; and a second LC resonator coupled to the substrate and comprising a second coupling point, a second capacitive element electrically coupled between the second coupling point and the first conductive region, and a second inductive element electrically coupled between the second coupling point and the first conductive region wherein the system group delays a signal output at a second coupling point relative to a signal input at the first coupling point.

First claim

We claim:

1. A time delay filter comprising:
a substrate comprising a first isolative layer, the first isolative layer comprising a first surface and a second surface, the second surface substantially parallel to the first surface;
a resonator, comprising a capacitive element coupled to an inductive element, the inductive element comprising:
a first conductive region coupled to the first surface of the first isolative layer,
a second conductive region coupled to the second surface of the first isolative layer,
a first via that is electrically coupled to and extends between the first and second conductive region;
a second via that is electrically coupled to and extends between the first conductive region and a first portion of the capacitive element;
a third via that is electrically coupled to and extends between the second conductive region and a second portion of the capacitive element;

wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via form a loop;
a first coupling point, electrically coupled to the first conductive region of the resonator; and
a second coupling point, electrically coupled to the second conductive region of the resonator.

2. The system of claim 1 , wherein the first portion of the capacitive element comprises a first conductive planar region, the second portion of the capacitive element comprises a second conductive planar region, and the first and second portions are substantially parallel.

3. The system of claim 2 , wherein the first and second sides of the capacitive element are separated by a dielectric layer of the substrate, wherein the dielectric layer comprises hafnium oxide.

4. The system of claim 2 , wherein the first conductive planar region comprises a first and second subregion, wherein the first and second subregions are electrically isolated; wherein the second conductive planar region comprises a third and fourth subregion, wherein the third and fourth subregions are electrically isolated; and wherein a projected area of third subregion overlaps a projected area of the first subregion and overlaps a projected area of the second subregion.

5. The system of claim 4 , further comprising a first and second tapping point, wherein the first tapping point is electrically coupled to the third subregion and the second tapping point is electrically coupled to the second subregion.

6. The system of claim 5 , wherein the substrate comprises a conductive layer between the first and second surfaces, and wherein the conductive layer is electrically coupled to the first via at a point between the first surface and the second surface; and further comprising a third tapping point electrically coupled to the conductive layer.

7. The system of claim 1 , wherein the first conductive region comprises a strip inductor that extends over a first area of the first surface, and wherein the second conductive region comprises a ground plane that extends over a second area of the second surface, wherein the second area is greater than the first area.

8. The system of claim 1 , wherein the substrate comprises a conductive layer between the first and second surfaces of the isolative layer, and wherein the conductive layer is electrically connected to the first via at a point between the first surface and the second surface; and further comprising a tapping point electrically connected to the conductive layer.

9. The system of claim 8 , further comprising a second tapping point electrically connected to the first via at a second point between the first surface and the second surface, and a switch that resistively couples the first tapping point and the first coupling point when in a first switch state and resistively couples the second tapping point to the first coupling point when in a second switch state.

10. A time delay filter comprising:
a substrate comprising a first surface and a second surface opposite the first surface; wherein the first surface comprises a first conductive region;
a first LC resonator coupled to the substrate and comprising:
a first coupling point,
a first capacitive element electrically coupled between the first coupling point and the first conductive region, and
a first inductive element electrically coupled between the first coupling point and the first conductive region, and comprising:
a first and second inductor tap;
a second conductive region coupled to the second surface,
a first via that is electrically connected to and extends between the first and second conductive regions;
a second via that is electrically connected to and extends between the first conductive region and a first portion of the capacitive element;

wherein the first and second inductor taps are resistively coupled to the second via; and
a third via that is electrically connected to and extends between the second conductive region and a second portion of the capacitive element;

wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via define a loop;

a first switch that couples the first inductor tap to the first coupling point when in a first switch state and couples the second inductor tap to the first coupling point when in a second switch state;

wherein the inductive element has a first inductance when the first switch is in the first switch state and a second inductance when the first switch is in the second switch state; and
a second LC resonator coupled to the substrate and comprising:
a second coupling point,
a second capacitive element electrically coupled between the second coupling point and the first conductive region, and
a second inductive element electrically coupled between the second coupling point and the first conductive region;

wherein the system group delays a signal output at the second coupling point relative to a signal input at the first coupling point.

11. The system of claim 10 , wherein the first and second LC resonators are electrically connected in parallel between an input matching element and an output matching element.

12. The system of claim 10 , wherein the first and second LC resonators have identical frequency responses.

13. The system of claim 10 , further comprising a tunable capacitor, coupled between the first coupling point and the second coupling point.

14. The system of claim 10 , wherein the first and second coupling points are resistively coupled.

15. The system of claim 10 , wherein, during operation, the first inductive element of the first LC resonator is electromagnetically coupled to the second inductive element of the second LC resonator.

16. The system of claim 15 , further comprising a capacitive element, electrically coupled between the first coupling point and the second coupling point.

17. The system of claim 10 , wherein the first inductive element comprises a plurality of inductive subelements connected in parallel, wherein the plurality of inductive subelements are in a braided configuration.

18. The system of claim 10 , further comprising: a third LC resonator, coupled to the substrate and electrically coupled to the first conductive region and comprising a third inductive element, a third capacitive element, and a third coupling point; and a fourth LC resonator, coupled to the substrate and electrically coupled to the first conductive region and comprising a fourth inductive element, a fourth capacitive element, and a fourth coupling point.

19. The system of

Assignees

• Kumu Networks Inc

Inventors

• Hahn Wilhelm Steffen
• Riddle Alfred
• Landi Ernie

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H03H7/345

  Adjustable networks · CPC title

• H03H7/34

  with lumped and distributed reactance · CPC title

• H03H7/0115

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03H2001/0085

  Multilayer, e.g. LTCC, HTCC, green sheets · CPC title