Tunable duplexing circuit

US9819324B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9819324-B2
Application numberUS-201615182412-A
CountryUS
Kind codeB2
Filing dateJun 14, 2016
Priority dateFeb 4, 2014
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A tunable duplexer circuit is described, wherein the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. A method is described where the duplexer circuit characteristics are optimized in conjunction with a specific antenna frequency response to provide additional out-of-band rejection in a communication system. Dynamic optimization of both the duplexer circuit and an active antenna system is described to provide improved out-of-band rejection when implemented in RF front-end circuits of communication systems. Other features and embodiments are described in the following detailed descriptions.

First claim

Opening claim text (preview).

What is claimed is: 1. A tunable band-pass circuit comprising: a first tuning section comprising: a first inductor in series with a first tunable capacitor, the first tunable capacitor being further connected to ground; a second tuning section comprising: a second inductor, a first phase shifter, and a second tunable capacitor in a series configuration, with the second tunable capacitor being further connected to ground; a third inductor connected in parallel across the second inductor and first phase shifter; a first fixed capacitor positioned between the second inductor and the third inductor; and a third tuning section comprising a fourth inductor and a second fixed capacitor in a series configuration forming a first series LC circuit; a fifth inductor and a third fixed capacitor in a series configuration forming a second series LC circuit; a sixth inductor in series with a third tunable capacitor forming a third series LC circuit, a first terminal end of the third series LC circuit connected to a common junction of the first and second series LC circuits, and a second terminal end of the third series LC circuit being connected to ground; a fourth fixed capacitor positioned between the first series LC circuit and the second series LC circuit; the first, second, and third tuning sections being connected in series between a first port and a second port to form a band-pass frequency response; wherein each of the first through third tunable capacitors is configured for variable tuning for changing the frequency response of the circuit. 2. The tunable band pass circuit of claim 1 , wherein at least one of the first through sixth inductors comprises a tunable inductor. 3. A tunable duplexer, said tunable duplexer comprising: a first tunable band-pass circuit, the first tunable band-pass circuit comprising: a first tuning section comprising: a first inductor in series with a first tunable capacitor, the first tunable capacitor being further connected to ground; a second tuning section comprising: a second inductor, a first phase shifter, and a second tunable capacitor in a series configuration, with the second tunable capacitor being further connected to ground; a third inductor connected in parallel across the second inductor and first phase shifter; a first fixed capacitor positioned between the second inductor and the third inductor; and a third tuning section comprising a fourth inductor and a second fixed capacitor in a series configuration forming a first series LC circuit; a fifth inductor and a third fixed capacitor in a series configuration forming a second series LC circuit; a sixth inductor in series with a third tunable capacitor forming a third series LC circuit, a first terminal end of the third series LC circuit connected to a common junction of the first and second series LC circuits, and a second terminal end of the third series LC circuit being connected to ground; a fourth fixed capacitor positioned between the first series LC circuit and the second series LC circuit; the first, second, and third tuning sections being connected in series between a first port and a second port to form a band-pass frequency response; a second tunable band-pass circuit; and memory comprising a lookup table, said lookup table containing data for configuring one or more or the tunable capacitors of the tunable duplexer; said first and second tunable band-pass circuits coupled at a common input port. 4. The tunable duplexer of claim 3 , wherein the first tunable band-pass circuit further comprises a transmit port formed at an end opposite the common input port. 5. The tunable duplexer of claim 3 , wherein the second tunable band-pass circuit further comprises a receive port formed at an end opposite the common input port. 6. The tunable duplexer of claim 3 , combined with a second tunable duplexer and a third tunable duplexer; wherein the input ports of the first and second tunable duplexers are each connected to a first and second output port of the third tunable duplexer to form a tunable quadplexer. 7. The tunable duplexer of claim 3 , wherein each of the first through third tunable capacitors is configured for variable tuning for changing the frequency response of the circuit. 8. The tunable duplexer of claim 3 , wherein the second tuning section further comprises: a second phase shifter in series with the second inductor, the first phase shifter, and the second tunable capacitor. 9. The tunable duplexer of claim 8 , further comprising a first switch connected in parallel to the first phase shifter. 10. The tunable duplexer of claim 9 , wherein the third inductor is connected in parallel across the second inductor and first and second phase shifters.

Assignees

Inventors

Classifications

  • Networks for phase shifting · CPC title

  • Networks for phase shifting · CPC title

  • having variable circuit topology, e.g. including switches · CPC title

  • H03H7/0161Primary

    Bandpass filters (H03H7/12 takes precedence) · CPC title

  • Series LC in shunt or branch path (H03H7/1791 takes precedence) · CPC title

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Frequently asked questions

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What does patent US9819324B2 cover?
A tunable duplexer circuit is described, wherein the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. A method is described where the duplexer circ…
Who is the assignee on this patent?
Ethertronics Inc
What technology area does this patent fall under?
Primary CPC classification H03H7/0161. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).