Time delay unit comprising a spirally wound meandering line pattern

US9819068B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9819068-B2
Application numberUS-201414482077-A
CountryUS
Kind codeB2
Filing dateSep 10, 2014
Priority dateSep 10, 2014
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic stripline circuit includes a flexible dielectric film having a three-dimensional coiled shape that defines a spiraled inner core. At least one electrically conductive signal trace is formed on a first surface of the flexible dielectric film. The signal trace extends along a signal path to define a trace length configured to control a time delay of a coiled time delay unit.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic stripline circuit, comprising: a flexible dielectric film having a three-dimensional coiled shape that defines a spiraled inner core; at least one electrically conductive signal trace formed on a first surface of the flexible dielectric film, the signal trace extending along a signal path to define a trace length configured to control a time delay of a coiled time delay unit, the at least one signal trace having a meandering pattern that extends between a first terminal end and a second terminal end formed on the stripline circuit; and a dielectric layer disposed on the at least one signal trace, wherein the flexible dielectric film comprises: a first metal clad layer having a ground plane formed thereon; and a second metal clad layer including the at least one signal trace formed thereon. 2. The stripline circuit of claim 1 , wherein the dielectric layer is formed from a flexible liquid crystal polymer material. 3. The stripline circuit of claim 2 , wherein a second dielectric layer covers a first portion of the flexible dielectric film while exposing a second portion of the flexible dielectric film. 4. The stripline circuit of claim 3 , wherein the exposed second portion is located between the dielectric layer and the first and second terminal ends. 5. The stripline circuit of claim 4 , wherein the first terminal end and the second terminal end are disposed on a common side of the flexible dielectric film. 6. The stripline circuit of claim 5 , wherein the at least one signal trace meanders between the first and second terminal ends, and in a direction extending along a width of the flexible dielectric film to form a plurality of lengthwise portions extending perpendicular to the width, the lengthwise portions separated by each other by a respective bent portion extending perpendicular to the lengthwise portions. 7. The stripline circuit of claim 6 , wherein the flexible dielectric film is formed from a liquid crystal polymer (LCP). 8. A time delay unit, comprising: an electrically conductive stripline including at least one electrically conductive signal trace formed thereon, the stripline having a three-dimensional coiled shape that defines a spiraled inner core and including a flexible dielectric film having the at least one signal trace formed therein; a printed wiring board including at least one electrically conductive board trace in conductive contact with the at least one signal trace; and a dielectric layer disposed on the at least one signal trace, wherein the flexible dielectric film comprises: a first metal clad layer having a ground plane formed thereon; and a second metal clad layer including the at least one signal trace formed thereon, the signal trace having a meandering pattern that extends between a first terminal end and a second terminal end. 9. The time delay unit of claim 8 , wherein the at least one board trace includes a first board trace having a first proximate end connected to the first terminal end, and a second board trace having a second proximate end connected to the second terminal end. 10. The time delay unit of claim 9 , wherein a first distal end of the first board trace and a second distal end of the second board trace are each connected to an RF antenna. 11. The time delay unit of claim 10 , wherein the time delay unit is configured to provide a time delay value that controls the frequency range of the RF antenna. 12. The time delay unit of claim 11 , wherein the time delay unit includes at least one edge wrap formed on a respective end of the stripline, the at least one edge wrap configured to minimize the distance between the ground layer of the flexible dielectric film and the ground layer of the board. 13. The time delay unit of claim 12 , wherein the at least one edge wrap includes a first edge wrap formed on a first end of the stripline and a second edge wrap formed on a second end of the stripline opposite the first end, the first and second edge wraps connecting together the ground layers of the stripline.

Assignees

Inventors

Classifications

  • Helical lines · CPC title

  • H01P9/006Primary

    Meander lines · CPC title

  • Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

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Frequently asked questions

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What does patent US9819068B2 cover?
An electronic stripline circuit includes a flexible dielectric film having a three-dimensional coiled shape that defines a spiraled inner core. At least one electrically conductive signal trace is formed on a first surface of the flexible dielectric film. The signal trace extends along a signal path to define a trace length configured to control a time delay of a coiled time delay unit.
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification H01P9/006. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).