Semiconductor device, optical sensor device and semiconductor device manufacturing method

Patent metadata

Field	Value
Publication number	US-9818895-B2
Application number	US-201514694278-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Jun 3, 2010
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1 , and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z≧−0.4x+24.6 is satisfied.

First claim

The invention claimed is:

1. A semiconductor device formed on an InP substrate, comprising:
an absorption layer of a type II multiple quantum well structure, located on the InP substrate, wherein
the multiple quantum well structure is a strain-compensated structure composed of a repetition of a GaAs 1-x Sb x layer and an In y Ga 1-y As layer, and
the GaAs 1-x Sb x layer has an Sb composition x (at. %) and a thickness z (nm) which satisfy relationships (1) to (2) below:
44 at. %≦ x≦ 54.3 at. %, and  (1)

7 nm≦ z< 10 nm,  (2)

wherein in a maximum wavelength at which the absorption layer has detectivity is not shorter than 2.4 μm, and
wherein the Sb composition x of the GaAs 1-x Sb x layer and an In composition y (at. %) of the In x Ga 1-y As layer satisfy 100≦x+y≦104.

2. The semiconductor device according to claim 1 , including an InP contact layer on the multiple quantum well structure.

3. The semiconductor device according to claim 1 , wherein when, in the multiple quantum well structure, a lattice mismatch of the In y Ga 1-y As layer is Δω 1 and a lattice mismatch of the GaAs 1-x Sb x layer is Δω 2 , a lattice mismatch Δω of the entire multiple quantum well structure is defined by Δω={Σ(Δω 1 ×thickness of the In y Ga 1-y As layer+Δω 2 ×thickness of the GaAs 1-x Sb x layer)}/{Σ(thickness of the In y Ga 1-y As layer+thickness of the GaAs 1-x Sb x layer)}, and the Δω is not smaller than −0.2% but not greater than 0.2%.

4. The semiconductor device according to claim 3 , wherein there is no regrown interface between a bottom surface of the absorption layer and an upper surface of a semiconductor layer including the absorption layer and the InP contact layer.

5. An optical sensor device adopting, as a photodiode, the semiconductor device according to claim 1 .

6. A method of manufacturing a semiconductor device on an InP substrate, comprising:
a step of forming an absorption layer of a type II multiple quantum well structure on the InP substrate, wherein
the multiple quantum well structure is a strain-compensated structure composed of a GaAs 1-x Sb x layer and an In y Ga 1-y As layer, and
in the step of forming the multiple quantum well structure, an Sb composition x (at. %) and a thickness z (nm) of the GaAs 1-x Sb x layer satisfy relationships (1) to (2) below:
44 at. %≦ x≦ 54.3 at. %, and  (1)

7 nm≦ z< 10 nm,  (2)

wherein in a maximum wavelength at which the absorption layer has detectivity is not shorter than 2.4 μm, and
wherein the Sb composition x of the GaAs 1-x Sb x layer and an In composition y (at. %) of the In y GaAs 1-y layer satisfy 100≦x+y≦104.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein an In composition y (at. %) of the In y Ga 1-y As layer is decreased at a rate of 0.9 to 1.2 per increase of 1 at. % of the Sb composition x of the GaAs 1-x Sb x layer.

8. The method of manufacturing a semiconductor device according to claim 6 , wherein in the step of forming the multiple quantum well structure, the multiple quantum well structure is formed at a temperature not lower than 400° C. but not higher than 560° C.

Assignees

• Sumitomo Electric Industries

Inventors

• Fujii Kei
• Akita Katsushi
• Ishizuka Takashi
• Nakahata Hideaki
• Iguchi Yasuhiro
• Inada Hiroshi
• Nagai Youichi

Classifications

• H01L31/035236 Primary

  Electricity · mapped topic

• B82Y20/00

  Nanooptics, e.g. quantum optics or photonic crystals · CPC title

• H01L31/03046

  Electricity · mapped topic

• H01L31/1844

  Electricity · mapped topic

• H01L31/105

  Electricity · mapped topic