Solar cell module and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9818891-B2
Application number	US-201514985113-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Dec 31, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A solar cell module and a method for manufacturing the same are disclosed. The method for manufacturing the solar cell module includes applying a low melting point metal on an electrode included in each of a plurality of solar cells, melting the low melting point metal to form a contact layer on the electrode, generating an ultrasonic vibration in the contact layer to remove a surface oxide layer formed on a surface of the electrode, melting a surface metal of the electrode and the contact layer to form a metal connection layer on the surface of the electrode, and connecting the metal connection layer to an interconnector.

First claim

What is claimed is:

1. A method for manufacturing a solar cell module comprising:
applying a first low melting point metal layer of a metal solder on a first electrode and a second electrode included on a tope surface in each of a plurality of solar cells;
melting the first low melting point metal layer to form a contact layer on the first electrode;
generating an ultrasonic vibration in the contact layer to remove a surface oxide layer formed on a surface of the first electrode while keeping an insulating layer disposed between a surface of the second electrode and the first low melting point metal layer;
melting a surface metal of the first electrode and the contact layer to form a metal connection layer on the surface of the first electrode; and
connecting the metal connection layer to a second low melting point metal layer of an interconnector.

2. The method of claim 1 , wherein the removing of the surface oxide layer includes:
generating the ultrasonic vibration in a surface of the contact layer;
generating a cavitation phenomenon inside the contact layer by the ultrasonic vibration; and
removing the surface oxide layer formed on the surface of the first electrode by the cavitation phenomenon.

3. The method of claim 1 , wherein the connecting of the metal connection layer to the second low melting point metal layer of the interconnector includes melting a first low melting point metal of the metal connection layer and a second low melting point metal of the interconnector and bonding the metal connection layer to the interconnector.

4. The method of claim 1 , wherein the ultrasonic vibration is generated by an ultrasonic tip.

5. The method of claim 1 , further comprising, before applying the first low melting point metal layer, forming an insulating layer surrounding the first electrode.

6. The method of claim 1 , further comprising forming the first electrode and the second electrode, wherein the forming of the first electrode and the second electrode includes:
applying a first metal on a first surface of a semiconductor substrate;
generating the ultrasonic vibration in the first metal to form the first electrode;
applying a second metal on a second surface of the semiconductor substrate; and
generating the ultrasonic vibration in the second metal to form the second electrode.

7. The method of claim 6 , wherein the first metal is a high melting point metal, and the second metal is a low melting point metal.

8. The method of claim 7 , wherein a melting point of the high melting point metal is equal to or higher than about 150° C., and a melting point of the low melting point metal is equal to or lower than about 150° C.

9. The method of claim 8 , wherein the high melting point metal includes at least one conductive material of Sn—Ag—Cu, Sn—Zn, or Sn—Pb.

10. The method of claim 8 , wherein an amount of tin (Sn) included in the high melting point metal is about 60 wt % to 100 wt %, and
wherein an amount of tin (Sn) included in the low melting point metal is about 10 wt % to 60 wt %.

11. The method of claim 6 , further comprising, before forming the first and second electrodes, forming a first anti-reflection layer on the first surface of the semiconductor substrate and forming a second anti-reflection layer on the second surface of the semiconductor substrate.

12. The method of claim 11 , wherein the forming of the first electrode includes:
generating a cavitation phenomenon by the ultrasonic vibration to etch a portion of the first anti-reflection layer; and
connecting the first metal to the first surface of the semiconductor substrate through the etched portion of the first anti-reflection layer.

13. The method of claim 11 , wherein the forming of the second electrode includes:
generating a cavitation phenomenon by the ultrasonic vibration to etch a portion of the second anti-reflection layer; and
connecting the second metal to the second surface of the semiconductor substrate through the etched portion of the second anti-reflection layer.

14. The method of claim 12 , further comprising forming a first connection layer between the first surface of the semiconductor substrate and the first electrode.

15. The method of claim 14 , wherein the first connection layer is formed by generating cracks inside the first anti-reflection layer by the cavitation phenomenon.

16. The method of claim 15 , wherein the first connection layer is formed by mixing the first anti-reflection layer with the first metal.

17. The method of claim 13 , further comprising forming a second connection layer between the second surface of the semiconductor substrate and the second electrode.

18. The method of claim 17 , wherein the second connection layer is formed by generating cracks inside the second anti-reflection layer by the cavitation phenomenon.

19. The method of claim 18 , wherein the second connection layer is formed by mixing the second anti-reflection layer with the second metal.

20. The method of claim 6 , wherein the first surface is a non-incident surface, on which light is not incident, and
wherein the second surface is an incident surface, on which light is incident.

Assignees

• Lg Electronics Inc

Inventors

• Lim Kwangyoung
• Moon Kangseok
• Son Jeonghun
• Ahn Sehwon

Classifications

• H01L31/0516

  Electricity · mapped topic

• H01L31/0508

  Electricity · mapped topic

• H01L31/0504

  Electricity · mapped topic

• H01L31/022425 Primary

  Electricity · mapped topic

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title