Dynamic threshold MOS and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9818842-B2
Application number	US-201615255731-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	Oct 2, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.

First claim

What is claimed is:

1. A method comprising:
forming first isolation regions extending from a back surface of a substrate into the substrate, wherein the substrate comprises a semiconductor material;
implanting the substrate to form a well pickup region extending from the back surface of the substrate to a well region in the substrate;
forming a transistor at a front surface of the substrate, wherein the forming the transistor comprises:
forming a source/drain region extending into the substrate, wherein a bottom surface of the source/drain region contacts a top surface of the first isolation regions; and

forming second isolation regions extending from the front surface of the substrate to the first isolation regions.

2. The method of claim 1 further comprising:
implanting the substrate to form a hydrogen-concentrated layer extending deeper into the substrate than the first isolation regions and a portion of the well region; and
separating portions of the substrate on opposite sides of the hydrogen-concentrated layer from each other.

3. The method of claim 1 further comprising forming a through-via penetrating through the substrate, wherein the through-via electrically interconnects a gate electrode of the transistor and the well pickup region.

4. The method of claim 3 , wherein the forming the through-via comprises:
forming an opening extending from the front surface to the back surface of the substrate;
forming an isolation layer in the opening; and
filling a metallic material in the opening.

5. The method of claim 4 , wherein the opening penetrates through one of the first isolation regions or one of the second isolation regions.

6. The method of claim 4 , wherein the opening penetrates through both one of the first isolation regions and one of the second isolation regions.

7. The method of claim 1 further comprising forming the well region comprising a portion at a same level as the first isolation regions.

8. The method of claim 1 further comprising bonding a first wafer comprising the substrate to a second wafer, wherein when the bonding is performed, the first wafer is mounted on a carrier, with an adhesive between and in contact with the carrier and the well pickup region.

9. A method comprising:
forming a composite isolation region extending from a first surface to a second surface of a substrate, wherein the first surface and the second surface are opposite surfaces of the substrate, wherein the substrate comprises a semiconductor material;
forming a gate dielectric and a gate electrode on the first surface of the substrate;
forming a well pickup region extending from the second surface of the substrate into the substrate, with a well region having a portion between the gate dielectric and the well pickup region;
forming an opening to penetrate through the substrate; and
filling the opening with a metallic material to form a through-via, wherein the through-via electrically inter-couples the gate electrode and the well pickup region.

10. The method of claim 9 , wherein the forming the composite isolation region comprises:
forming a first isolation region extending from the second surface of the substrate to an intermediate level between the first surface and the second surface of the substrate; and
forming a second isolation region extending from the first surface of the substrate to the first isolation region.

11. The method of claim 10 , wherein the first isolation region and the second isolation region are formed in different processes.

12. The method of claim 10 , wherein the first isolation region and the second isolation region have a distinguishable interface.

13. The method of claim 10 , wherein the forming the opening comprises etching both the first isolation region and the second isolation region.

14. The method of claim 9 , wherein a first surface of the composite isolation region is substantially coplanar with a surface of the gate dielectric, and a second surface of the composite isolation region is substantially coplanar with a surface of the well pickup region.

15. A method comprising:
forming a first isolation region and a second isolation region extending from a first surface of a substrate into the substrate, wherein the substrate comprises a semiconductor material;
forming a well pickup region between the first isolation region and the second isolation region;
forming a well region comprising:
a first portion between the first isolation region and the second isolation region, wherein the first portion of the well region is at a same level as the first isolation region and the second isolation region; and
a second portion extending deeper into the substrate than the first isolation region;

revealing the second portion of the well region;
forming a transistor on the second portion of the well region, wherein the transistor is formed on a second surface of the substrate; and
forming a through-via extending from the first surface to the second surface of the substrate, with the through-via electrically inter-coupling the transistor and the well pickup region.

16. The method of claim 15 , wherein the revealing the second portion of the well region comprises removing a portion of the substrate deeper in the substrate than the second portion of the well region.

17. The method of claim 16 , wherein the removing the portion of the substrate comprises:
implanting the substrate to form a hydrogen-concentrated layer, with the hydrogen-concentrated layer extending deeper into the substrate than the second portion of the well region; and
removing the portion of the substrate by separating portions of the substrate on opposite sides of the hydrogen-concentrated layer from each other.

18. The method of claim 15 further comprising forming an isolation layer encircling the through-via, wherein the isolation layer is in physical contact with the semiconductor material of the substrate.

19. The method of claim 15 , wherein the through-via is formed from a first side of the substrate, with the first surface being facing the first side.

20. The method of claim 19 , wherein the through-via is wider on the first side than on an opposite second side.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Jam-Wem

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title