Semiconductor substrate and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-9818824-B2
Application number	US-201514968049-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Jan 23, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a base substrate;
a first silicon germanium layer on the base substrate;
a second silicon germanium layer on the first silicon germanium layer, a germanium fraction of the second silicon germanium layer decreasing in a direction away from the base substrate, and the germanium fraction of the second silicon germanium layer at a lowermost part thereof being greater than a germanium fraction of an uppermost part of the first silicon germanium layer; and
a gate electrode disposed on the second silicon germanium layer.

2. The semiconductor device of claim 1 , further comprising a channel layer on the second silicon germanium layer and under the gate electrode,
wherein the channel layer comprises silicon, germanium, silicon germanium, and/or a group III-V compound semiconductor.

3. The semiconductor device of claim 1 , further comprising:
a fin type active pattern on the second silicon germanium layer and a channel layer on the fin active pattern,
wherein
the gate electrode is disposed on the channel layer so as to intersect with the fin type active pattern.

4. The semiconductor device of claim 3 , further comprising:
source/drain regions at both sides of the gate electrode,
wherein each of the source/drain regions includes an epitaxial layer formed on the fin type active pattern.

5. The semiconductor device of claim 3 , wherein the fin type active pattern includes silicon germanium having a constant germanium fraction over a thickness thereof.

6. The semiconductor device of claim 1 , further comprising:
a third silicon germanium layer between the second silicon germanium layer and a channel layer,
wherein a germanium fraction of a lowermost part of the third silicon germanium layer is greater than the germanium fraction of the uppermost part of the first silicon germanium layer, and wherein the germanium fraction of the second silicon germanium layer at the lowermost part thereof is greater than a germanium fraction of an uppermost part of the third silicon germanium layer.

7. The semiconductor device of claim 6 , wherein the channel layer includes silicon germanium, and
a germanium fraction of the channel layer is greater than the germanium fraction of the third silicon germanium layer.

8. The semiconductor device of claim 1 , further comprising:
a third silicon germanium layer having a constant germanium fraction over a thickness thereof between a channel layer and the base substrate.

9. The semiconductor device of claim 1 , further comprising:
a third silicon germanium layer between a channel layer and the base substrate, the third silicon germanium layer having a germanium fraction which decreases in the direction away from the base substrate.

10. The semiconductor device of claim 1 , wherein the base substrate includes a silicon substrate.

11. A semiconductor device comprising:
a substrate comprising a base layer and a first silicon germanium layer on the base layer;
a fin type active pattern which protrudes from the substrate and includes silicon germanium, a part of a side wall of the fin type active patterns being covered with a field insulating film;
a channel layer on the fin type active pattern;
a gate electrode on the channel layer, the gate electrode intersecting the fin type active pattern; and
an epitaxial layer formed on the side wall of the fin type active pattern at a side of the gate electrode,
wherein a germanium fraction of the first silicon germanium layer decreases in a direction away from the base layer, and the germanium fraction of the first silicon germanium layer at a lowermost part thereof is greater than a germanium fraction of an uppermost part of the base layer.

12. The semiconductor device of claim 11 , wherein the epitaxial layer is formed along a profile of the fin type active pattern protruding above an upper surface of the field insulating film.

13. The semiconductor device of claim 12 , wherein the channel layer extends between the epitaxial layer and the fin type active pattern.

14. The semiconductor device of claim 13 , further comprising:
a source/drain region within the epitaxial layer, the channel layer and the fin type active pattern.

15. The semiconductor device of claim 11 , wherein the substrate further includes a second silicon germanium layer formed on the first silicon germanium layer, and
the second silicon germanium layer has a constant germanium fraction over a thickness thereof.

16. The semiconductor device of claim 15 , wherein the second silicon germanium layer and the fin type active pattern are an integral structure.

17. The semiconductor device of claim 16 , wherein the germanium fraction of the second silicon germanium layer is greater than the germanium fraction of the first silicon germanium layer at an uppermost part thereof.

18. The semiconductor device of claim 15 , wherein the base layer includes a silicon substrate, and a third silicon germanium layer on the silicon substrate, and
the germanium fraction of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the third silicon germanium layer.

19. The semiconductor device of claim 11 , wherein the base layer includes a silicon substrate, and a second silicon germanium layer on the silicon substrate, and a germanium fraction of an uppermost part of the second silicon germanium layer is smaller than the germanium fraction of the first silicon germanium layer at the lowermost part thereof, and further comprising a third silicon germanium layer on the first silicon germanium layer opposite the second silicon germanium layer, wherein the germanium fraction of the lowermost part of the first silicon germanium layer is greater than a germanium fraction of an uppermost part of the third silicon germanium layer.

20. The semiconductor device of claim 11 , further comprising:
an insulating film pattern disposed within the substrate.

21. A semiconductor device, comprising:
a substrate;
a strain released layer on the substrate, the strain released layer having a lattice constant that is larger than a lattice constant of a directly underlying layer at an interface therewith; and
a strain relaxed buffer layer directly on the strain released layer opposite the underlying layer,
wherein the lattice constant of the strain released layer decreases from the interface with the underlying layer to an interface with the strain relaxed buffer layer directly thereon, and wherein the strain released layer, the underlying layer, and the strain relaxed buffer layer comprise a same compound semiconductor material.

22. The semiconductor device of claim 21 , wherein the lattice constant of the strain released layer decreases continuously or in a stepwise manner from the interface with the underlying layer to the interface with the strain relaxed buffer layer directly thereon.

23. The semiconductor device of claim 22 , wherein a lattice constant of the strain relaxed buffer layer is substantially uniform over a thickness thereof.

24. The semiconductor device of claim 22 , wherein a lattice constant of the strain relaxed buffer layer at the interface with the strain released layer is larger than, smaller than, or equal to the lattice constant of the underlying layer, and wherein the lattice constant of the strain released layer at the interface with the underlying layer is larger than a lattice constant of the strai

Assignees

• Yang Moon Seung
• Choi Eun Hye
• Kim Sun Jung
• Lee Seung Hun
• Lee Hyun-Jung
• Samsung Electronics Co Ltd

Inventors

• Yang Moon Seung
• Choi Eun Hye
• Kim Sun Jung
• Lee Seung Hun
• Lee Hyun-Jung

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title