Defect reduction using aspect ratio trapping

Patent metadata

Field	Value
Publication number	US-9818819-B2
Application number	US-201615088634-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Sep 7, 2006
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.

First claim

What is claimed is:

1. A structure comprising:
a substrate comprising a first crystalline semiconductor material, the substrate having a major top surface and a recess portion, the recess portion including faceted surfaces of the first crystalline semiconductor material;
a dielectric layer disposed over the substrate, the dielectric layer having an opening to the substrate that defines a first portion of the first crystalline semiconductor material, the first portion including faceted surfaces of the first crystalline semiconductor material; and
a second semiconductor material disposed in the opening, the second semiconductor material being lattice mismatched to the first crystalline semiconductor material, the second semiconductor material comprising a lattice defect, the lattice defect terminating at a first sidewall of the opening, the first sidewall defining a first angle with at least one of the faceted surfaces of the first crystalline semiconductor material, the first angle being less than 90°, the first sidewall extending above and away from the major top surface of the substrate.

2. The structure of claim 1 , wherein the faceted surfaces of the substrate are (111) surfaces of the substrate, the substrate comprising silicon.

3. The structure of claim 1 , wherein the second semiconductor material has a top surface coplanar with a top surface of the dielectric layer.

4. A structure comprising:
a substrate comprising a first semiconductor material;
an insulator layer disposed over a top surface of the substrate and defining a trench having two sidewalls, each of the two sidewalls comprising a sloped sidewall portion extending in a direction away from the other sloped sidewall portion, each of the two sloped sidewall portions having a first angle relative a line perpendicular to a top surface of the substrate, the first angle being from 6° to 12° or from 25° to 40°; and
a second semiconductor material disposed in the trench, the second semiconductor material being lattice mismatched to the first semiconductor material, wherein a portion of the second semiconductor material comprises lattice defects, a first plurality of the lattice defects terminating at the sidewall, each of the first plurality of lattice defects terminating at the sidewall at an angle a with the sidewall, the angle being 45° or less.

5. The structure of claim 4 , wherein each of the first plurality of lattice defects have a first portion and a second portion, the first portion being in a first direction, the second portion being in a second direction different from the first direction and non-parallel to the top surface of the substrate, the second portions of the first plurality of lattice defects terminating at the two sidewalls.

6. The structure of claim 4 , wherein the insulator layer has a height in a direction perpendicular to the top surface of the substrate, the trench having a length in a direction parallel to the top surface of the substrate, the length being greater than the height.

7. The structure of claim 4 , wherein the insulator layer has a height in a direction perpendicular to the top surface of the substrate, the trench having a width in a direction parallel to the top surface of the substrate, the width being equal to or less than twice the height.

8. The structure of claim 4 , wherein the trench has a length in a direction parallel to the top surface of the substrate, the trench having a width in a direction parallel to the top surface of the substrate, the length being at least twice the width.

9. The structure of claim 4 , wherein the second semiconductor material comprises a group IV element or compound, a III-V compound, or a II-VI compound.

10. The structure of claim 9 , wherein the substrate comprises germanium and/or silicon.

11. A method comprising:
forming a dielectric sidewall on a substrate, the substrate comprising a first crystalline semiconductor material and having a top surface, the dielectric sidewall comprises at least a lower portion that is sloped and an upper portion that is perpendicular to the top surface of the substrate; and
epitaxially growing a second crystalline semiconductor material on the substrate and adjoining the dielectric sidewall, the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, a dislocation in the second crystalline semiconductor material arising from the lattice mismatch, the dislocation being directed to the dielectric sidewall in a direction approximately perpendicular to a growth front of the second crystalline semiconductor material, the dislocation terminating at the dielectric sidewall in the direction, the dislocation defining an angle a with the dielectric sidewall, the angle being 45° or less.

12. The method of claim 11 , wherein the direction is within 10° of perpendicular to the growth front.

13. The method of claim 11 , wherein the growth front comprises a facet.

14. The method of claim 11 , wherein the growth front comprises a convex surface.

15. The method of claim 11 further comprising:
forming a dielectric layer over the top surface of the substrate, an opening being defined through the dielectric layer, the dielectric sidewall being a sidewall of the opening.

16. The structure of claim 1 , wherein the faceted surfaces are recessed from the major top surface of the substrate.

17. The structure of claim 1 , wherein the dielectric layer contacts a bottommost surface of the recess portion of the first crystalline semiconductor material.

18. The method of claim 11 , wherein the dislocation terminates at the upper portion the dielectric sidewall.

19. The method of claim 11 , wherein the second crystalline semiconductor material comprises a group IV element or compound, a III-V compound, or a II-VI compound.

20. The method of claim 11 , wherein the first crystalline semiconductor material comprises germanium and/or silicon.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Bai Jie
• Lochtefeld Anthony J
• Park Ji-Soo

Classifications

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title